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25bbbd2d63
Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
31 lines
1.2 KiB
C
31 lines
1.2 KiB
C
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_N2_H
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#define NEOVERSE_N2_H
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/* Neoverse N2 ID register for revision r0p0 */
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#define NEOVERSE_N2_MIDR U(0x410FD490)
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/*******************************************************************************
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* CPU Power control register
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******************************************************************************/
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#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#endif /* NEOVERSE_N2_H */
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