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2590e819eb
MPMM is a core-specific microarchitectural feature. It has been present in every Arm core since the Cortex-A510 and has been implemented in exactly the same way. Despite that, it is enabled more like an architectural feature with a top level enable flag. This utilised the identical implementation. This duality has left MPMM in an awkward place, where its enablement should be generic, like an architectural feature, but since it is not, it should also be core-specific if it ever changes. One choice to do this has been through the device tree. This has worked just fine so far, however, recent implementations expose a weakness in that this is rather slow - the device tree has to be read, there's a long call stack of functions with many branches, and system registers are read. In the hot path of PSCI CPU powerdown, this has a significant and measurable impact. Besides it being a rather large amount of code that is difficult to understand. Since MPMM is a microarchitectural feature, its correct placement is in the reset function. The essence of the current enablement is to write CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C enablement with an assembly macro in each CPU's reset function achieves the same effect with just a single close branch and a grand total of 6 instructions (versus the old 2 branches and 32 instructions). Having done this, the device tree entry becomes redundant. Should a core that doesn't support MPMM arise, this can cleanly be handled in the reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks mechanisms become obsolete and are removed. Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
178 lines
5.7 KiB
ArmAsm
178 lines
5.7 KiB
ArmAsm
/*
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x4.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_prologue cortex_x4
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.global check_erratum_cortex_x4_2726228
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.global check_erratum_cortex_x4_3701758
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
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#endif /* WORKAROUND_CVE_2022_23960 */
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add_erratum_entry cortex_x4, ERRATUM(2726228), ERRATA_X4_2726228
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check_erratum_ls cortex_x4, ERRATUM(2726228), CPU_REV(0, 1)
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x4, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X4_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x4, CVE(2024, 5660)
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check_erratum_ls cortex_x4, CVE(2024, 5660), CPU_REV(0, 2)
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workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_x4, ERRATUM(2740089)
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check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018
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sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47)
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workaround_reset_end cortex_x4, ERRATUM(2763018)
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check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013
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mrs x1, id_aa64pfr1_el1
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ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4
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cbz x2, #1f
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sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14)
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1:
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workaround_reset_end cortex_x4, ERRATUM(2816013)
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check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2897503), ERRATA_X4_2897503
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sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, BIT(8)
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workaround_reset_end cortex_x4, ERRATUM(2897503)
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check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985
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sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10))
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workaround_reset_end cortex_x4, ERRATUM(2923985)
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check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2957258), ERRATA_X4_2957258
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/* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */
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ldr x0, =0x1
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msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
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ldr x0, =0xd5380000
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msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
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ldr x0, =0xFFFFFF40
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msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
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ldr x0, =0x000080010033f
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msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
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isb
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workaround_reset_end cortex_x4, ERRATUM(2957258)
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check_erratum_ls cortex_x4, ERRATUM(2957258), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789
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sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14)
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sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13)
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sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52)
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workaround_reset_end cortex_x4, ERRATUM(3076789)
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check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex X4 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_x4
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_x4, CVE(2022, 23960)
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check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set CORTEX_X4_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end cortex_x4, CVE(2024, 7881)
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check_erratum_chosen cortex_x4, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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add_erratum_entry cortex_x4, ERRATUM(3701758), ERRATA_X4_3701758
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check_erratum_ls cortex_x4, ERRATUM(3701758), CPU_REV(0, 3)
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cpu_reset_func_start cortex_x4
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/* Disable speculative loads */
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msr SSBS, xzr
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enable_mpmm
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cpu_reset_func_end cortex_x4
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x4_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV
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isb
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ret
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endfunc cortex_x4_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex X4-specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x4_regs, "aS"
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cortex_x4_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x4_cpu_reg_dump
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adr x6, cortex_x4_regs
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mrs x8, CORTEX_X4_CPUECTLR_EL1
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ret
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endfunc cortex_x4_cpu_reg_dump
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declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \
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cortex_x4_reset_func, \
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CPU_NO_EXTRA1_FUNC, \
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CPU_NO_EXTRA2_FUNC, \
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CPU_NO_EXTRA3_FUNC, \
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check_erratum_cortex_x4_7881, \
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cortex_x4_core_pwr_dwn
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