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2590e819eb
MPMM is a core-specific microarchitectural feature. It has been present in every Arm core since the Cortex-A510 and has been implemented in exactly the same way. Despite that, it is enabled more like an architectural feature with a top level enable flag. This utilised the identical implementation. This duality has left MPMM in an awkward place, where its enablement should be generic, like an architectural feature, but since it is not, it should also be core-specific if it ever changes. One choice to do this has been through the device tree. This has worked just fine so far, however, recent implementations expose a weakness in that this is rather slow - the device tree has to be read, there's a long call stack of functions with many branches, and system registers are read. In the hot path of PSCI CPU powerdown, this has a significant and measurable impact. Besides it being a rather large amount of code that is difficult to understand. Since MPMM is a microarchitectural feature, its correct placement is in the reset function. The essence of the current enablement is to write CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C enablement with an assembly macro in each CPU's reset function achieves the same effect with just a single close branch and a grand total of 6 instructions (versus the old 2 branches and 32 instructions). Having done this, the device tree entry becomes redundant. Should a core that doesn't support MPMM arise, this can cleanly be handled in the reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks mechanisms become obsolete and are removed. Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
277 lines
9.3 KiB
ArmAsm
277 lines
9.3 KiB
ArmAsm
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a710.h>
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#include <cpu_macros.S>
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#include <dsu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global check_erratum_cortex_a710_3701772
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue cortex_a710
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a710, CVE(2024, 5660)
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check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1)
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workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
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ldr x0,=0x6
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xF3A08002
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFF0F7FE
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x40000001003ff
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msr S3_6_c15_c8_1,x0
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ldr x0,=0x7
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xBF200000
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0000
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x40000001003f3
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msr S3_6_c15_c8_1,x0
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workaround_reset_end cortex_a710, ERRATUM(1987031)
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check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0)
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workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
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/* Stash ERRSELR_EL1 in x2 */
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mrs x2, ERRSELR_EL1
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/* Select error record 0 and clear ED bit */
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msr ERRSELR_EL1, xzr
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mrs x1, ERXCTLR_EL1
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bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
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msr ERXCTLR_EL1, x1
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/* Select error record 1 and clear ED bit */
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mov x0, #1
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msr ERRSELR_EL1, x0
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mrs x1, ERXCTLR_EL1
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bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
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msr ERXCTLR_EL1, x1
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/* Restore ERRSELR_EL1 from x2 */
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msr ERRSELR_EL1, x2
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workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB
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check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096
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sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
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workaround_reset_end cortex_a710, ERRATUM(2017096)
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check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002
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sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46
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workaround_reset_end cortex_a710, ERRATUM(2055002)
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check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056
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sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \
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CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH
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workaround_reset_end cortex_a710, ERRATUM(2058056)
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check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1)
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workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180
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ldr x0,=0x3
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xF3A08002
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFF0F7FE
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x10002001003FF
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msr S3_6_c15_c8_1,x0
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ldr x0,=0x4
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xBF200000
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0000
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x10002001003F3
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msr S3_6_c15_c8_1,x0
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workaround_reset_end cortex_a710, ERRATUM(2081180)
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check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908
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sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
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workaround_reset_end cortex_a710, ERRATUM(2083908)
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check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059
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sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
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workaround_reset_end cortex_a710, ERRATUM(2136059)
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check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715
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sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
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workaround_reset_end cortex_a710, ERRATUM(2147715)
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check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384
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sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17
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ldr x0,=0x5
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msr CORTEX_A710_CPUPSELR_EL3, x0
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ldr x0,=0x10F600E000
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msr CORTEX_A710_CPUPOR_EL3, x0
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ldr x0,=0x10FF80E000
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msr CORTEX_A710_CPUPMR_EL3, x0
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ldr x0,=0x80000000003FF
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msr CORTEX_A710_CPUPCR_EL3, x0
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workaround_reset_end cortex_a710, ERRATUM(2216384)
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check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065
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sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22
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workaround_reset_end cortex_a710, ERRATUM(2267065)
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check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622
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sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0)
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workaround_reset_end cortex_a710, ERRATUM(2282622)
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check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1)
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.global erratum_cortex_a710_2291219_wa
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workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219
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/* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying
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* the workaround. Second call clears it to undo it. */
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sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36
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workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB
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check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941
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errata_dsu_2313941_wa_impl
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workaround_reset_end cortex_a710, ERRATUM(2313941)
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check_erratum_custom_start cortex_a710, ERRATUM(2313941)
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check_errata_dsu_2313941_impl
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ret
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check_erratum_custom_end cortex_a710, ERRATUM(2313941)
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workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105
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/* Set bit 40 in CPUACTLR2_EL1 */
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sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40
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workaround_reset_end cortex_a710, ERRATUM(2371105)
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check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0)
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workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423
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/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
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sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55)
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sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56)
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workaround_reset_end cortex_a710, ERRATUM(2742423)
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check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1)
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workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB
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check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1)
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workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471
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sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47)
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workaround_reset_end cortex_a710, ERRATUM(2778471)
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check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1)
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workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A710 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_a710
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a710, CVE(2022, 23960)
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check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772
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check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a710_core_pwr_dwn
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apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV
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apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV
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isb
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ret
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endfunc cortex_a710_core_pwr_dwn
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cpu_reset_func_start cortex_a710
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/* Disable speculative loads */
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msr SSBS, xzr
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enable_mpmm
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cpu_reset_func_end cortex_a710
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/* ---------------------------------------------
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* This function provides Cortex-A710 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a710_regs, "aS"
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cortex_a710_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a710_cpu_reg_dump
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adr x6, cortex_a710_regs
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mrs x8, CORTEX_A710_CPUECTLR_EL1
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ret
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endfunc cortex_a710_cpu_reg_dump
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declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \
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cortex_a710_reset_func, \
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cortex_a710_core_pwr_dwn
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