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https://github.com/ARM-software/arm-trusted-firmware.git
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b07c317f67
Similar to the reset function inline, inline this too to not do a costly branch with no extra cost. Change-Id: I54cc399e570e9d0f373ae13c7224d32dbdfae1e5 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
490 lines
17 KiB
ArmAsm
490 lines
17 KiB
ArmAsm
/*
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* Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef EL3_COMMON_MACROS_S
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#define EL3_COMMON_MACROS_S
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <context.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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/*
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* Helper macro to initialise EL3 registers we care about.
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*/
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.macro el3_arch_init_common
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/* ---------------------------------------------------------------------
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* SCTLR_EL3 has already been initialised - read current value before
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* modifying.
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*
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* SCTLR_EL3.I: Enable the instruction cache.
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*
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* SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
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* exception is generated if a load or store instruction executed at
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* EL3 uses the SP as the base address and the SP is not aligned to a
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* 16-byte boundary.
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*
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* SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
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* load or store one or more registers have an alignment check that the
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* address being accessed is aligned to the size of the data element(s)
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* being accessed.
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* ---------------------------------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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#ifdef IMAGE_BL31
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/* ---------------------------------------------------------------------
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* Initialise the per-cpu cache pointer to the CPU.
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* This is done early to enable crash reporting to have access to crash
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* stack. Since crash reporting depends on cpu_data to report the
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* unhandled exception, not doing so can lead to recursive exceptions
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* due to a NULL TPIDR_EL3.
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* ---------------------------------------------------------------------
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*/
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bl plat_my_core_pos
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bl _cpu_data_by_index
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msr tpidr_el3, x0
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#endif /* IMAGE_BL31 */
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/* ---------------------------------------------------------------------
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* Initialise SCR_EL3, setting all fields rather than relying on hw.
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* All fields are architecturally UNKNOWN on reset. The following fields
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* do not change during the TF lifetime. The remaining fields are set to
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* zero here but are updated ahead of transitioning to a lower EL in the
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* function cm_init_context_common().
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*
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* SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled.
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*
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* NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate
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* against ERRATA_V2_3099206.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, SCR_RESET_VAL
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#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
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mrs x1, id_aa64pfr0_el1
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and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
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cbz x1, 1f
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orr x0, x0, #SCR_EEL2_BIT
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#endif
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1:
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msr scr_el3, x0
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/* ---------------------------------------------------------------------
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* Initialise MDCR_EL3, setting all fields rather than relying on hw.
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* Some fields are architecturally UNKNOWN on reset.
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*/
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mov_imm x0, MDCR_EL3_RESET_VAL
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msr mdcr_el3, x0
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/* ---------------------------------------------------------------------
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* Initialise CPTR_EL3, setting all fields rather than relying on hw.
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* All fields are architecturally UNKNOWN on reset.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, CPTR_EL3_RESET_VAL
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msr cptr_el3, x0
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.endm
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/* -----------------------------------------------------------------------------
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* This is the super set of actions that need to be performed during a cold boot
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* or a warm boot in EL3. This code is shared by BL1 and BL31.
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*
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* This macro will always perform reset handling, architectural initialisations
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* and stack setup. The rest of the actions are optional because they might not
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* be needed, depending on the context in which this macro is called. This is
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* why this macro is parameterised ; each parameter allows to enable/disable
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* some actions.
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*
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* _init_sctlr:
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* Whether the macro needs to initialise SCTLR_EL3, including configuring
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* the endianness of data accesses.
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*
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* _warm_boot_mailbox:
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* Whether the macro needs to detect the type of boot (cold/warm). The
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* detection is based on the platform entrypoint address : if it is zero
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* then it is a cold boot, otherwise it is a warm boot. In the latter case,
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* this macro jumps on the platform entrypoint address.
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*
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* _secondary_cold_boot:
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* Whether the macro needs to identify the CPU that is calling it: primary
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* CPU or secondary CPU. The primary CPU will be allowed to carry on with
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* the platform initialisations, while the secondaries will be put in a
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* platform-specific state in the meantime.
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*
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* If the caller knows this macro will only be called by the primary CPU
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* then this parameter can be defined to 0 to skip this step.
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*
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* _init_memory:
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* Whether the macro needs to initialise the memory.
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*
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* _init_c_runtime:
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* Whether the macro needs to initialise the C runtime environment.
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*
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* _exception_vectors:
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* Address of the exception vectors to program in the VBAR_EL3 register.
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*
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* _pie_fixup_size:
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* Size of memory region to fixup Global Descriptor Table (GDT).
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*
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* A non-zero value is expected when firmware needs GDT to be fixed-up.
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*
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* -----------------------------------------------------------------------------
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*/
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.macro el3_entrypoint_common \
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_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
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_init_memory, _init_c_runtime, _exception_vectors, \
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_pie_fixup_size
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.if \_init_sctlr
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/* -------------------------------------------------------------
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* This is the initialisation of SCTLR_EL3 and so must ensure
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* that all fields are explicitly set rather than relying on hw.
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* Some fields reset to an IMPLEMENTATION DEFINED value and
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* others are architecturally UNKNOWN on reset.
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*
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* SCTLR.EE: Set the CPU endianness before doing anything that
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* might involve memory reads or writes. Set to zero to select
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* Little Endian.
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*
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* SCTLR_EL3.WXN: For the EL3 translation regime, this field can
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* force all memory regions that are writeable to be treated as
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* XN (Execute-never). Set to zero so that this control has no
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* effect on memory access permissions.
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*
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* SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
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*
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* SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
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*
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* SCTLR.DSSBS: Set to zero to disable speculation store bypass
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* safe behaviour upon exception entry to EL3.
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* -------------------------------------------------------------
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*/
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mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
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| SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
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#if ENABLE_FEAT_RAS
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/* If FEAT_RAS is present assume FEAT_IESB is also present */
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orr x0, x0, #SCTLR_IESB_BIT
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#endif
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msr sctlr_el3, x0
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isb
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.endif /* _init_sctlr */
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.if \_warm_boot_mailbox
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/* -------------------------------------------------------------
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* This code will be executed for both warm and cold resets.
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* Now is the time to distinguish between the two.
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* Query the platform entrypoint address and if it is not zero
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* then it means it is a warm boot so jump to this address.
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* -------------------------------------------------------------
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*/
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bl plat_get_my_entrypoint
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cbz x0, do_cold_boot
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br x0
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do_cold_boot:
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.endif /* _warm_boot_mailbox */
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.if \_pie_fixup_size
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#if ENABLE_PIE
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/*
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* ------------------------------------------------------------
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* If PIE is enabled fixup the Global descriptor Table only
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* once during primary core cold boot path.
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*
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* Compile time base address, required for fixup, is calculated
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* using "pie_fixup" label present within first page.
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* ------------------------------------------------------------
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*/
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pie_fixup:
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ldr x0, =pie_fixup
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and x0, x0, #~(PAGE_SIZE_MASK)
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mov_imm x1, \_pie_fixup_size
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add x1, x1, x0
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bl fixup_gdt_reloc
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#endif /* ENABLE_PIE */
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.endif /* _pie_fixup_size */
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/* ---------------------------------------------------------------------
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* Set the exception vectors.
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* ---------------------------------------------------------------------
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*/
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adr x0, \_exception_vectors
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msr vbar_el3, x0
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isb
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call_reset_handler
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el3_arch_init_common
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/* ---------------------------------------------------------------------
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* Set the el3 execution context(i.e. root_context).
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* ---------------------------------------------------------------------
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*/
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setup_el3_execution_context
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.if \_secondary_cold_boot
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/* -------------------------------------------------------------
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* Check if this is a primary or secondary CPU cold boot.
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* The primary CPU will set up the platform while the
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* secondaries are placed in a platform-specific state until the
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* primary CPU performs the necessary actions to bring them out
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* of that state and allows entry into the OS.
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* -------------------------------------------------------------
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*/
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bl plat_is_my_cpu_primary
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cbnz w0, do_primary_cold_boot
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/* This is a cold boot on a secondary CPU */
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bl plat_secondary_cold_boot_setup
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/* plat_secondary_cold_boot_setup() is not supposed to return */
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bl el3_panic
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do_primary_cold_boot:
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.endif /* _secondary_cold_boot */
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/* ---------------------------------------------------------------------
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* Initialize memory now. Secondary CPU initialization won't get to this
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* point.
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* ---------------------------------------------------------------------
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*/
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.if \_init_memory
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bl platform_mem_init
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.endif /* _init_memory */
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/* ---------------------------------------------------------------------
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* Init C runtime environment:
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* - Zero-initialise the NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section (if any).
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* - Relocate the data section from ROM to RAM, if required.
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* ---------------------------------------------------------------------
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*/
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.if \_init_c_runtime
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#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \
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((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME))
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/* -------------------------------------------------------------
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* Invalidate the RW memory used by the BL31 image. This
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* includes the data and NOBITS sections. This is done to
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* safeguard against possible corruption of this memory by
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* dirty cache lines in a system cache as a result of use by
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* an earlier boot loader stage. If PIE is enabled however,
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* RO sections including the GOT may be modified during
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* pie fixup. Therefore, to be on the safe side, invalidate
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* the entire image region if PIE is enabled.
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* -------------------------------------------------------------
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*/
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#if ENABLE_PIE
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#if SEPARATE_CODE_AND_RODATA
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adrp x0, __TEXT_START__
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add x0, x0, :lo12:__TEXT_START__
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#else
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adrp x0, __RO_START__
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add x0, x0, :lo12:__RO_START__
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#endif /* SEPARATE_CODE_AND_RODATA */
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#else
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adrp x0, __RW_START__
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add x0, x0, :lo12:__RW_START__
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#endif /* ENABLE_PIE */
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adrp x1, __RW_END__
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add x1, x1, :lo12:__RW_END__
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sub x1, x1, x0
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bl inv_dcache_range
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#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION
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adrp x0, __NOBITS_START__
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add x0, x0, :lo12:__NOBITS_START__
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adrp x1, __NOBITS_END__
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add x1, x1, :lo12:__NOBITS_END__
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sub x1, x1, x0
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bl inv_dcache_range
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#endif
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#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION
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adrp x0, __BL2_NOLOAD_START__
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add x0, x0, :lo12:__BL2_NOLOAD_START__
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adrp x1, __BL2_NOLOAD_END__
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add x1, x1, :lo12:__BL2_NOLOAD_END__
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sub x1, x1, x0
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bl inv_dcache_range
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#endif
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#endif
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adrp x0, __BSS_START__
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add x0, x0, :lo12:__BSS_START__
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adrp x1, __BSS_END__
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add x1, x1, :lo12:__BSS_END__
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sub x1, x1, x0
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bl zeromem
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#if USE_COHERENT_MEM
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adrp x0, __COHERENT_RAM_START__
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add x0, x0, :lo12:__COHERENT_RAM_START__
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adrp x1, __COHERENT_RAM_END_UNALIGNED__
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add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
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sub x1, x1, x0
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bl zeromem
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#endif
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#if defined(IMAGE_BL1) || \
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(defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM) || \
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(defined(IMAGE_BL31) && SEPARATE_RWDATA_REGION)
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adrp x0, __DATA_RAM_START__
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add x0, x0, :lo12:__DATA_RAM_START__
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adrp x1, __DATA_ROM_START__
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add x1, x1, :lo12:__DATA_ROM_START__
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adrp x2, __DATA_RAM_END__
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add x2, x2, :lo12:__DATA_RAM_END__
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sub x2, x2, x0
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bl memcpy16
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#endif
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.endif /* _init_c_runtime */
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/* ---------------------------------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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* ---------------------------------------------------------------------
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*/
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msr spsel, #0
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/* ---------------------------------------------------------------------
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* Allocate a stack whose memory will be marked as Normal-IS-WBWA when
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* the MMU is enabled. There is no risk of reading stale stack memory
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* after enabling the MMU as only the primary CPU is running at the
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* moment.
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* ---------------------------------------------------------------------
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*/
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bl plat_set_my_stack
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#if STACK_PROTECTOR_ENABLED
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.if \_init_c_runtime
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bl update_stack_protector_canary
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.endif /* _init_c_runtime */
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#endif
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.endm
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.macro apply_at_speculative_wa
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#if ERRATA_SPECULATIVE_AT
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/*
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* This function expects x30 has been saved.
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* Also, save x29 which will be used in the called function.
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*/
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str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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bl save_and_update_ptw_el1_sys_regs
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ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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#endif
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.endm
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.macro restore_ptw_el1_sys_regs
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#if ERRATA_SPECULATIVE_AT
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/* -----------------------------------------------------------
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* In case of ERRATA_SPECULATIVE_AT, must follow below order
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* to ensure that page table walk is not enabled until
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* restoration of all EL1 system registers. TCR_EL1 register
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* should be updated at the end which restores previous page
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* table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB
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* ensures that CPU does below steps in order.
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*
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* 1. Ensure all other system registers are written before
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* updating SCTLR_EL1 using ISB.
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* 2. Restore SCTLR_EL1 register.
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* 3. Ensure SCTLR_EL1 written successfully using ISB.
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* 4. Restore TCR_EL1 register.
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* -----------------------------------------------------------
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*/
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isb
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ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1]
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msr sctlr_el1, x28
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isb
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msr tcr_el1, x29
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#endif
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.endm
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/* -----------------------------------------------------------------
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* The below macro reads SCR_EL3 from the context structure to
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* determine the security state of the context upon ERET.
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* ------------------------------------------------------------------
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*/
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.macro get_security_state _ret:req, _scr_reg:req
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ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1
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cmp \_ret, #1
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beq realm_state
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bfi \_ret, \_scr_reg, #0, #1
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b end
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realm_state:
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mov \_ret, #2
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end:
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.endm
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/*-----------------------------------------------------------------------------
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* Helper macro to configure EL3 registers we care about, while executing
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* at EL3/Root world. Root world has its own execution environment and
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* needs to have its settings configured to be independent of other worlds.
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* -----------------------------------------------------------------------------
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*/
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.macro setup_el3_execution_context
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/* ---------------------------------------------------------------------
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* The following registers need to be part of separate root context
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* as their values are of importance during EL3 execution.
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* Hence these registers are overwritten to their intital values,
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* irrespective of whichever world they return from to ensure EL3 has a
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* consistent execution context throughout the lifetime of TF-A.
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*
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* DAIF.A: Enable External Aborts and SError Interrupts at EL3.
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*
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* MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
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* Debug exceptions, other than Breakpoint Instruction exceptions, are
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* disabled from all ELs in Secure state.
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*
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* SCR_EL3.EA: Set to one to enable SError interrupts at EL3.
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*
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* SCR_EL3.SIF: Set to one to disable instruction fetches from
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* Non-secure memory.
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*
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* PMCR_EL0.DP: Set to one so that the cycle counter,
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* PMCCNTR_EL0 does not count when event counting is prohibited.
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* Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not
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* available.
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*
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* PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT)
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* functionality, if implemented in EL3.
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* ---------------------------------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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mrs x15, mdcr_el3
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orr x15, x15, #MDCR_SDD_BIT
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msr mdcr_el3, x15
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mrs x15, scr_el3
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orr x15, x15, #SCR_EA_BIT
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orr x15, x15, #SCR_SIF_BIT
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msr scr_el3, x15
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mrs x15, pmcr_el0
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orr x15, x15, #PMCR_EL0_DP_BIT
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msr pmcr_el0, x15
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#if ENABLE_FEAT_DIT
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#if ENABLE_FEAT_DIT > 1
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|
mrs x15, id_aa64pfr0_el1
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ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
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|
cbz x15, 1f
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|
#endif
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mov x15, #DIT_BIT
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|
msr DIT, x15
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|
1:
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#endif
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|
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isb
|
|
.endm
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|
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#endif /* EL3_COMMON_MACROS_S */
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