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2590e819eb
MPMM is a core-specific microarchitectural feature. It has been present in every Arm core since the Cortex-A510 and has been implemented in exactly the same way. Despite that, it is enabled more like an architectural feature with a top level enable flag. This utilised the identical implementation. This duality has left MPMM in an awkward place, where its enablement should be generic, like an architectural feature, but since it is not, it should also be core-specific if it ever changes. One choice to do this has been through the device tree. This has worked just fine so far, however, recent implementations expose a weakness in that this is rather slow - the device tree has to be read, there's a long call stack of functions with many branches, and system registers are read. In the hot path of PSCI CPU powerdown, this has a significant and measurable impact. Besides it being a rather large amount of code that is difficult to understand. Since MPMM is a microarchitectural feature, its correct placement is in the reset function. The essence of the current enablement is to write CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C enablement with an assembly macro in each CPU's reset function achieves the same effect with just a single close branch and a grand total of 6 instructions (versus the old 2 branches and 32 instructions). Having done this, the device tree entry becomes redundant. Should a core that doesn't support MPMM arise, this can cleanly be handled in the reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks mechanisms become obsolete and are removed. Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
293 lines
6.2 KiB
Text
293 lines
6.2 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <platform_def.h>
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#if TARGET_FLAVOUR_FVP
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#define LIT_CAPACITY 406
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#define MID_CAPACITY 912
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#else /* TARGET_FLAVOUR_FPGA */
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#define LIT_CAPACITY 280
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#define MID_CAPACITY 775
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/* this is an area optimized configuration of the big core */
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#define BIG2_CAPACITY 930
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#endif /* TARGET_FLAVOUR_FPGA */
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#define BIG_CAPACITY 1024
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#define MHU_TX_ADDR 45000000 /* hex */
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#define MHU_TX_COMPAT "arm,mhuv2-tx","arm,primecell"
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#define MHU_TX_INT_NAME "mhu_tx"
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#define MHU_RX_ADDR 45010000 /* hex */
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#define MHU_RX_COMPAT "arm,mhuv2-rx","arm,primecell"
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#define MHU_OFFSET 0x1000
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#define MHU_MBOX_CELLS 2
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#define MHU_RX_INT_NUM 317
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#define MHU_RX_INT_NAME "mhu_rx"
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#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
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#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu"
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#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
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#define DSU_MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
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#define DPU_ADDR 2cc00000
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#define DPU_IRQ 69
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#define ETHERNET_ADDR 18000000
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#define ETHERNET_INT 109
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#define SYS_REGS_ADDR 1c010000
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#define MMC_ADDR 1c050000
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#define MMC_INT_0 107
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#define MMC_INT_1 108
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#define RTC_ADDR 1c170000
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#define RTC_INT 100
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#define KMI_0_ADDR 1c060000
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#define KMI_0_INT 197
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#define KMI_1_ADDR 1c070000
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#define KMI_1_INT 103
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#define VIRTIO_BLOCK_ADDR 1c130000
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#define VIRTIO_BLOCK_INT 204
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#include "tc-common.dtsi"
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#if TARGET_FLAVOUR_FVP
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#include "tc-fvp.dtsi"
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#else
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#include "tc-fpga.dtsi"
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#endif /* TARGET_FLAVOUR_FVP */
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#include "tc-base.dtsi"
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/ {
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cpus {
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#if TARGET_FLAVOUR_FPGA
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cpu-map {
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cluster0 {
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core8 {
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cpu = <&CPU8>;
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};
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core9 {
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cpu = <&CPU9>;
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};
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core10 {
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cpu = <&CPU10>;
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};
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core11 {
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cpu = <&CPU11>;
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};
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core12 {
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cpu = <&CPU12>;
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};
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core13 {
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cpu = <&CPU13>;
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};
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};
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};
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#endif
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CPU2:cpu@200 {
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clocks = <&scmi_dvfs 0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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};
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CPU3:cpu@300 {
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clocks = <&scmi_dvfs 0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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};
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CPU6:cpu@600 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU7:cpu@700 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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#if TARGET_FLAVOUR_FPGA
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CPU8:cpu@800 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x800>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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amu = <&amu>;
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};
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CPU9:cpu@900 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x900>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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};
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CPU10:cpu@A00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xA00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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};
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CPU11:cpu@B00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xB00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG2_CAPACITY>;
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amu = <&amu>;
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};
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CPU12:cpu@C00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xC00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 3>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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amu = <&amu>;
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};
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CPU13:cpu@D00 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0xD00>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 3>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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amu = <&amu>;
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};
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#endif
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};
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#if TARGET_FLAVOUR_FPGA
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ete8 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU8>;
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};
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ete9 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU9>;
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};
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ete10 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU10>;
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};
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ete11 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU11>;
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};
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ete12 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU12>;
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};
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ete13 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU13>;
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};
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#endif /* TARGET_FLAVOUR_FPGA */
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cmn-pmu {
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compatible = "arm,ci-700";
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reg = <0x0 0x50000000 0x0 0x10000000>;
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interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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mbox_db_rx: mhu@MHU_RX_ADDR {
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arm,mhuv2-protocols = <0 1>;
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};
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mbox_db_tx: mhu@MHU_TX_ADDR {
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arm,mhuv2-protocols = <0 1>;
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};
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firmware {
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/*
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* TC2 does not have a P2A channel, but wiring one was needed to make Linux work
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* (by chance). At the time the SCMI driver did not support bidirectional
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* mailboxes so as a workaround, the A2P channel was wired for TX communication
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* and the synchronous replies would be read asyncrhonously as if coming from
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* the P2A channel, while being the actual A2P channel.
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*
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* This will not work with kernels > 5.15, but keep it around to keep TC2
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* working with its target kernel. Newer kernels will still work, but SCMI
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* won't as they check that the two regions are distinct.
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*/
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scmi {
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mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0>;
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shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_a2p>;
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};
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};
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gic: interrupt-controller@GIC_CTRL_ADDR {
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ppi-partitions {
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ppi_partition_little: interrupt-partition-0 {
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affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
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};
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#if TARGET_FLAVOUR_FVP
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ppi_partition_mid: interrupt-partition-1 {
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affinity = <&CPU4>, <&CPU5>, <&CPU6>;
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};
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ppi_partition_big: interrupt-partition-2 {
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affinity = <&CPU7>;
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};
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#elif TARGET_FLAVOUR_FPGA
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ppi_partition_mid: interrupt-partition-1 {
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affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, <&CPU8>;
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};
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ppi_partition_big: interrupt-partition-2 {
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affinity = <&CPU9>, <&CPU10>, <&CPU11>, <&CPU12>, <&CPU13>;
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};
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#endif
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};
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};
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spe-pmu-big {
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status = "okay";
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};
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smmu_700: iommu@3f000000 {
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status = "okay";
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};
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dp0: display@DPU_ADDR {
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#if TC_SCMI_PD_CTRL_EN
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power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
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#endif
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iommus = <&smmu_700 0x100>;
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};
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gpu: gpu@2d000000 {
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "JOB", "MMU", "GPU";
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iommus = <&smmu_700 0x200>;
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};
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};
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