mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-13 08:04:27 +00:00
2590e819eb
MPMM is a core-specific microarchitectural feature. It has been present in every Arm core since the Cortex-A510 and has been implemented in exactly the same way. Despite that, it is enabled more like an architectural feature with a top level enable flag. This utilised the identical implementation. This duality has left MPMM in an awkward place, where its enablement should be generic, like an architectural feature, but since it is not, it should also be core-specific if it ever changes. One choice to do this has been through the device tree. This has worked just fine so far, however, recent implementations expose a weakness in that this is rather slow - the device tree has to be read, there's a long call stack of functions with many branches, and system registers are read. In the hot path of PSCI CPU powerdown, this has a significant and measurable impact. Besides it being a rather large amount of code that is difficult to understand. Since MPMM is a microarchitectural feature, its correct placement is in the reset function. The essence of the current enablement is to write CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C enablement with an assembly macro in each CPU's reset function achieves the same effect with just a single close branch and a grand total of 6 instructions (versus the old 2 branches and 32 instructions). Having done this, the device tree entry becomes redundant. Should a core that doesn't support MPMM arise, this can cleanly be handled in the reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks mechanisms become obsolete and are removed. Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
676 lines
14 KiB
Text
676 lines
14 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* If SCMI power domain control is enabled */
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#if TC_SCMI_PD_CTRL_EN
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#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1)
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#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2)
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#endif /* TC_SCMI_PD_CTRL_EN */
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/* Use SCMI controlled clocks */
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#if TC_DPU_USE_SCMI_CLK
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#define DPU_CLK_ATTR1 \
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clocks = <&scmi_clk 0>; \
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clock-names = "aclk"
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#define DPU_CLK_ATTR2 \
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clocks = <&scmi_clk 1>; \
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clock-names = "pxclk"
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#define DPU_CLK_ATTR3 \
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clocks = <&scmi_clk 2>; \
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clock-names = "pxclk" \
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/* Use fixed clocks */
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#else /* !TC_DPU_USE_SCMI_CLK */
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#define DPU_CLK_ATTR1 \
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clocks = <&dpu_aclk>; \
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clock-names = "aclk"
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#define DPU_CLK_ATTR2 \
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clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \
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clock-names = "pxclk", "aclk"
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#define DPU_CLK_ATTR3 DPU_CLK_ATTR2
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#endif /* !TC_DPU_USE_SCMI_CLK */
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/ {
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compatible = "arm,tc";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &os_uart;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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/*
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* The timings below are just to demonstrate working cpuidle.
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* These values may be inaccurate.
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*/
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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local-timer-stop;
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entry-latency-us = <300>;
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exit-latency-us = <1200>;
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min-residency-us = <2000>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x1010000>;
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local-timer-stop;
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entry-latency-us = <400>;
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exit-latency-us = <1200>;
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min-residency-us = <2500>;
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};
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};
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amus {
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amu: amu-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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mpmm_gear0: counter@0 {
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reg = <0>;
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enable-at-el3;
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};
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mpmm_gear1: counter@1 {
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reg = <1>;
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enable-at-el3;
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};
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mpmm_gear2: counter@2 {
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reg = <2>;
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enable-at-el3;
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};
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};
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};
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CPU0:cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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amu = <&amu>;
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};
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CPU1:cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x100>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <LIT_CAPACITY>;
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amu = <&amu>;
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};
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CPU2:cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x200>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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amu = <&amu>;
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};
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CPU3:cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x300>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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amu = <&amu>;
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};
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CPU4:cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x400>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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amu = <&amu>;
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};
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CPU5:cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x500>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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amu = <&amu>;
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};
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CPU6:cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x600>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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amu = <&amu>;
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};
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CPU7:cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x700>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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amu = <&amu>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x8000000>;
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linux,cma-default;
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};
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optee {
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compatible = "restricted-dma-pool";
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reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
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<HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
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HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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cpu-pmu-little {
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compatible = LIT_CPU_PMU_COMPATIBLE;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>;
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status = "okay";
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};
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cpu-pmu-mid {
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compatible = MID_CPU_PMU_COMPATIBLE;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>;
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status = "okay";
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};
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cpu-pmu-big {
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compatible = BIG_CPU_PMU_COMPATIBLE;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>;
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status = "okay";
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};
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sram: sram@6000000 {
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compatible = "mmio-sram";
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reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>;
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cpu_scp_scmi_a2p: scp-shmem@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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};
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mbox_db_rx: mhu@MHU_RX_ADDR {
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compatible = MHU_RX_COMPAT;
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reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 MHU_OFFSET>;
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clocks = <&soc_refclk>;
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clock-names = "apb_pclk";
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#mbox-cells = <MHU_MBOX_CELLS>;
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interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = MHU_RX_INT_NAME;
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};
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mbox_db_tx: mhu@MHU_TX_ADDR {
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compatible = MHU_TX_COMPAT;
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reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 MHU_OFFSET>;
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clocks = <&soc_refclk>;
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clock-names = "apb_pclk";
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#mbox-cells = <MHU_MBOX_CELLS>;
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interrupt-names = MHU_TX_INT_NAME;
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};
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firmware {
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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#if TC_SCMI_PD_CTRL_EN
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scmi_devpd: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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#endif /* TC_SCMI_PD_CTRL_EN */
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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gic: interrupt-controller@GIC_CTRL_ADDR {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <4>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */
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interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW 0>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
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};
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spe-pmu-mid {
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compatible = "arm,statistical-profiling-extension-v1";
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interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>;
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status = "disabled";
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};
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spe-pmu-big {
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compatible = "arm,statistical-profiling-extension-v1";
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interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>;
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status = "disabled";
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};
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soc_refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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clock-output-names = "apb_pclk";
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};
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soc_refclk60mhz: refclk60mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <60000000>;
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clock-output-names = "iofpga_clk";
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};
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soc_uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <TC_UARTCLK>;
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clock-output-names = "uartclk";
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};
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/* soc_uart0 on FPGA, ap_ns_uart on FVP */
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os_uart: serial@2a400000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x2A400000 0x0 UART_OFFSET>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&soc_uartclk>, <&soc_refclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "okay";
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};
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#if !TC_DPU_USE_SCMI_CLK
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dpu_aclk: dpu_aclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <LCD_TIMING_CLK>;
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clock-output-names = "fpga:dpu_aclk";
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};
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dpu_pixel_clk: dpu-pixel-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <LCD_TIMING_CLK>;
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clock-output-names = "pxclk";
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};
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#endif /* !TC_DPU_USE_SCMI_CLK */
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#if TC_DPU_USE_SIMPLE_PANEL
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vpanel {
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compatible = "panel-dpi";
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post-init-providers = <&pl0>;
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port {
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lcd_in: endpoint {
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remote-endpoint = <&dp_pl0_out0>;
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};
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};
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panel-timing {
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LCD_TIMING;
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};
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};
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#else
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vencoder {
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compatible = "drm,virtual-encoder";
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port {
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lcd_in: endpoint {
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remote-endpoint = <&dp_pl0_out0>;
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};
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};
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display-timings {
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timing-panel {
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LCD_TIMING;
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};
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};
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};
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#endif
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ethernet: ethernet@ETHERNET_ADDR {
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reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>;
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interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>;
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reg-io-width = <2>;
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smsc,irq-push-pull;
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};
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bp_clock24mhz: clock24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "bp:clock24mhz";
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};
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sysreg: sysreg@SYS_REGS_ADDR {
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compatible = "arm,vexpress-sysreg";
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reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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fixed_3v3: v2m-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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mmci: mmci@MMC_ADDR {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>;
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interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>;
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wp-gpios = <&sysreg 1 0>;
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bus-width = <4>;
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max-frequency = <25000000>;
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vmmc-supply = <&fixed_3v3>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "mclk", "apb_pclk";
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};
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gpu_clk: gpu_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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};
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gpu_core_clk: gpu_core_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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};
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gpu: gpu@2d000000 {
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compatible = "arm,mali-midgard";
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reg = <0x0 0x2d000000 0x0 0x200000>;
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clocks = <&gpu_core_clk>;
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clock-names = "shadercores";
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#if TC_SCMI_PD_CTRL_EN
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power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>;
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scmi-perf-domain = <3>;
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#endif /* TC_SCMI_PD_CTRL_EN */
|
|
|
|
pbha {
|
|
int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>,
|
|
<8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>,
|
|
<12 0x22>, <13 0x22>, <16 0x22>, <17 0x32>,
|
|
<18 0x32>, <19 0x22>, <20 0x22>, <21 0x32>,
|
|
<22 0x32>, <24 0x22>, <28 0x32>;
|
|
propagate-bits = <0x0f>;
|
|
};
|
|
};
|
|
|
|
power_model_simple {
|
|
/*
|
|
* Numbers used are irrelevant to Titan,
|
|
* it helps suppressing the kernel warnings.
|
|
*/
|
|
compatible = "arm,mali-simple-power-model";
|
|
static-coefficient = <2427750>;
|
|
dynamic-coefficient = <4687>;
|
|
ts = <20000 2000 (-20) 2>;
|
|
thermal-zone = "";
|
|
};
|
|
|
|
smmu_600: smmu@2ce00000 {
|
|
compatible = "arm,smmu-v3";
|
|
reg = <0 0x2ce00000 0 0x20000>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING 0>,
|
|
<GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>,
|
|
<GIC_SPI 76 IRQ_TYPE_EDGE_RISING 0>,
|
|
<GIC_SPI 77 IRQ_TYPE_EDGE_RISING 0>;
|
|
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
smmu_700: iommu@3f000000 {
|
|
#iommu-cells = <1>;
|
|
compatible = "arm,smmu-v3";
|
|
reg = <0x0 0x3f000000 0x0 0x5000000>;
|
|
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING 0>,
|
|
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING 0>,
|
|
<GIC_SPI 230 IRQ_TYPE_EDGE_RISING 0>;
|
|
interrupt-names = "eventq", "cmdq-sync", "gerror";
|
|
dma-coherent;
|
|
status = "disabled";
|
|
};
|
|
|
|
smmu_700_dpu: iommu@4002a00000 {
|
|
#iommu-cells = <1>;
|
|
compatible = "arm,smmu-v3";
|
|
reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>;
|
|
interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING 0>,
|
|
<GIC_SPI 482 IRQ_TYPE_EDGE_RISING 0>,
|
|
<GIC_SPI 483 IRQ_TYPE_EDGE_RISING 0>;
|
|
interrupt-names = "eventq", "cmdq-sync", "gerror";
|
|
dma-coherent;
|
|
status = "disabled";
|
|
};
|
|
|
|
dp0: display@DPU_ADDR {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "arm,mali-d71";
|
|
reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>;
|
|
interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "DPU";
|
|
DPU_CLK_ATTR1;
|
|
|
|
pl0: pipeline@0 {
|
|
reg = <0>;
|
|
DPU_CLK_ATTR2;
|
|
pl_id = <0>;
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
dp_pl0_out0: endpoint {
|
|
remote-endpoint = <&lcd_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
pl1: pipeline@1 {
|
|
reg = <1>;
|
|
DPU_CLK_ATTR3;
|
|
pl_id = <1>;
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* L3 cache in the DSU is the Memory System Component (MSC)
|
|
* The MPAM registers are accessed through utility bus in the DSU
|
|
*/
|
|
dsu-msc0 {
|
|
compatible = "arm,mpam-msc";
|
|
reg = <DSU_MPAM_ADDR 0x0 0x2000>;
|
|
};
|
|
|
|
ete0 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU0>;
|
|
};
|
|
|
|
ete1 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU1>;
|
|
};
|
|
|
|
ete2 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU2>;
|
|
};
|
|
|
|
ete3 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU3>;
|
|
};
|
|
|
|
ete4 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU4>;
|
|
};
|
|
|
|
ete5 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU5>;
|
|
};
|
|
|
|
ete6 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU6>;
|
|
};
|
|
|
|
ete7 {
|
|
compatible = "arm,embedded-trace-extension";
|
|
cpu = <&CPU7>;
|
|
};
|
|
|
|
trbe {
|
|
compatible = "arm,trace-buffer-extension";
|
|
interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>;
|
|
};
|
|
|
|
trusty {
|
|
#size-cells = <0x02>;
|
|
#address-cells = <0x02>;
|
|
ranges = <0x00>;
|
|
compatible = "android,trusty-v1";
|
|
|
|
virtio {
|
|
compatible = "android,trusty-virtio-v1";
|
|
};
|
|
|
|
test {
|
|
compatible = "android,trusty-test-v1";
|
|
};
|
|
|
|
log {
|
|
compatible = "android,trusty-log-v1";
|
|
};
|
|
|
|
irq {
|
|
ipi-range = <0x08 0x0f 0x08>;
|
|
interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>;
|
|
interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>;
|
|
compatible = "android,trusty-irq-v1";
|
|
};
|
|
};
|
|
|
|
/* used in U-boot, Linux doesn't care */
|
|
arm_ffa {
|
|
compatible = "arm,ffa";
|
|
method = "smc";
|
|
};
|
|
};
|