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2537f0725e
Due to size constraints in OCM memory range keeping the bl31 with DEBUG=1 overlaps with the memory range from other Firmware thus affecting the bootflow on target. bl31 binary can not be placed in OCM memory range when built with DEBUG=1. With DEBUG=1, by default bl31 is moved to DDR memory range 0x1000-0x7FFFF. The user can provide a custom DDR memory range during build time using the build parameters ZYNQMP_ATF_MEM_BASE and ZYNQMP_ATF_MEM_SIZE. Change-Id: I167d5eadbae7c6d3ec9b32f494b0b1a819bea5b0 Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
88 lines
2.8 KiB
ReStructuredText
88 lines
2.8 KiB
ReStructuredText
Xilinx Zynq UltraScale+ MPSoC
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=============================
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq
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UltraScale + MPSoC.
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The platform only uses the runtime part of TF-A as ZynqMP already has a
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BootROM (BL1) and FSBL (BL2).
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BL31 is TF-A.
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BL32 is an optional Secure Payload.
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BL33 is the non-secure world software (U-Boot, Linux etc).
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To build:
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.. code:: bash
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make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31
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To build bl32 TSP you have to rebuild bl31 too:
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.. code:: bash
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make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd RESET_TO_BL31=1 bl31 bl32
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To build TF-A for JTAG DCC console:
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.. code:: bash
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make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc
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ZynqMP platform specific build options
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--------------------------------------
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- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary.
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- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary.
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- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary.
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- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary.
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- ``ZYNQMP_CONSOLE``: Select the console driver. Options:
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- ``cadence``, ``cadence0``: Cadence UART 0
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- ``cadence1`` : Cadence UART 1
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ZynqMP Debug behavior
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---------------------
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With DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range
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due to size constraints.
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For DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location
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of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF.
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If the user wants to move the bl31 to a different DDR location, user can provide
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the DDR address location in the build command as follows,
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make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
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ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> bl31
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FSBL->TF-A Parameter Passing
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----------------------------
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The FSBL populates a data structure with image information for TF-A. TF-A uses
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that data to hand off to the loaded images. The address of the handoff data
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structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The
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register is free to be used by other software once TF-A has brought up
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further firmware images.
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Power Domain Tree
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-----------------
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The following power domain tree represents the power domain model used by TF-A
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for ZynqMP:
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::
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+-+
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|0|
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+-+
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+-------+---+---+-------+
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v v v v
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+-+ +-+ +-+ +-+
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|0| |1| |2| |3|
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+-+ +-+ +-+ +-+
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The 4 leaf power domains represent the individual A53 cores, while resources
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common to the cluster are grouped in the power domain on the top.
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