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24fb838f96
This patch adds an optional platform API (plat_reset_handler) which allows the platform to perform any actions immediately after a cold or warm reset e.g. implement errata workarounds. The function is called with MMU and caches turned off. This API is weakly defined and does nothing by default but can be overriden by a platform with a strong definition. Change-Id: Ib0acdccbd24bc756528a8bd647df21e8d59707ff
109 lines
3.3 KiB
ArmAsm
109 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#if IMAGE_BL31
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#include <cpu_data.h>
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#endif
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/* Reset fn is needed in BL at reset vector */
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#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
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/*
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* The reset handler common to all platforms. After a matching
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* cpu_ops structure entry is found, the correponding reset_handler
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* in the cpu_ops is invoked.
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*/
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.globl reset_handler
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func reset_handler
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mov x10, x30
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bl plat_reset_handler
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/* Get the matching cpu_ops pointer */
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bl get_cpu_ops_ptr
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#if ASM_ASSERTION
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops reset handler */
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ldr x2, [x0, #CPU_RESET_FUNC]
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cbz x2, 1f
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blr x2
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1:
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ret x10
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#endif /* IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) */
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/*
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* The below function returns the cpu_ops structure matching the
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* midr of the core. It reads the MIDR_EL1 and finds the matching
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* entry in cpu_ops entries. Only the implementation and part number
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* are used to match the entries.
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* Return :
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* x0 - The matching cpu_ops pointer on Success
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* x0 - 0 on failure.
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* Clobbers : x0 - x5
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*/
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.globl get_cpu_ops_ptr
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func get_cpu_ops_ptr
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/* Get the cpu_ops start and end locations */
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adr x4, (__CPU_OPS_START__ + CPU_MIDR)
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adr x5, (__CPU_OPS_END__ + CPU_MIDR)
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/* Initialize the return parameter */
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mov x0, #0
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/* Read the MIDR_EL1 */
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mrs x2, midr_el1
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mov_imm x3, CPU_IMPL_PN_MASK
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/* Retain only the implementation and part number using mask */
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and w2, w2, w3
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1:
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/* Check if we have reached end of list */
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cmp x4, x5
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b.eq error_exit
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/* load the midr from the cpu_ops */
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ldr x1, [x4], #CPU_OPS_SIZE
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and w1, w1, w3
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/* Check if midr matches to midr of this core */
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cmp w1, w2
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b.ne 1b
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/* Subtract the increment and offset to get the cpu-ops pointer */
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sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR)
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error_exit:
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ret
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