Bipin Ravi b01a59eb2a fix(cpus): workaround for Cortex-A78C erratum 1827440 ... Cortex-A78C erratum 1827440 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[2], which forces atomic store operations to write-back memory to be performed in the L1 data cache. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I41d8ef48f70216ec66bf2b0f4f03ea8d8c261ee7		2023-03-21 16:21:38 -05:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	Cleanup the code for TBBR CoT descriptors	2020-05-19 05:05:19 +01:00
cpu-specific-build-macros.rst	fix(cpus): workaround for Cortex-A78C erratum 1827440	2023-03-21 16:21:38 -05:00
firmware-design.rst	refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3	2023-03-15 11:43:14 +00:00
index.rst	docs: add top level section numbering	2022-11-16 14:06:48 +00:00
interrupt-framework-design.rst	Fix broken links to various sections across docs	2020-08-03 09:55:04 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS	2022-04-29 22:54:34 +02:00
trusted-board-boot-build.rst	docs(arm): add ARM_ROTPK_LOCATION variant full key	2022-12-09 14:55:39 -06:00
trusted-board-boot.rst	fix: remove "experimental" tag for stable features	2021-10-22 10:49:20 +01:00