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https://github.com/ARM-software/arm-trusted-firmware.git
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3ca54cb4a3
Adapt to use errata frame-work cpu macro helpers for following cpu's: - Cortex-A7 - Cortex-A9 Testing: - Manual comparison of disassembly with and without the patch. - Compile testing. Change-Id: I88eb90d7fd0e82fc4bfc9d1aee947f0c820e1222 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
105 lines
2 KiB
ArmAsm
105 lines
2 KiB
ArmAsm
/*
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* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a9.h>
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#include <cpu_macros.S>
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.macro assert_cache_enabled
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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.endm
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func cortex_a9_disable_smp
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ldcopr r0, ACTLR
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bic r0, #CORTEX_A9_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a9_disable_smp
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func cortex_a9_enable_smp
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A9_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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bx lr
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endfunc cortex_a9_enable_smp
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func check_errata_794073
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#if ERRATA_A9_794073
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mov r0, #ERRATA_APPLIES
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#else
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mov r0, #ERRATA_MISSING
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#endif
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bx lr
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endfunc check_errata_794073
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add_erratum_entry cortex_a9, ERRATUM(794073), ERRATA_A9_794073
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func check_errata_cve_2017_5715
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#if WORKAROUND_CVE_2017_5715
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mov r0, #ERRATA_APPLIES
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#else
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mov r0, #ERRATA_MISSING
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#endif
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bx lr
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endfunc check_errata_cve_2017_5715
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add_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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errata_report_shim cortex_a9
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func cortex_a9_reset_func
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#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
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ldr r0, =wa_cve_2017_5715_bpiall_vbar
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stcopr r0, VBAR
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stcopr r0, MVBAR
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/* isb will be applied in the course of the reset func */
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#endif
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b cortex_a9_enable_smp
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endfunc cortex_a9_reset_func
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func cortex_a9_core_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 cache */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a9_disable_smp
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endfunc cortex_a9_core_pwr_dwn
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func cortex_a9_cluster_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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bl plat_disable_acp
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a9_disable_smp
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endfunc cortex_a9_cluster_pwr_dwn
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declare_cpu_ops cortex_a9, CORTEX_A9_MIDR, \
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cortex_a9_reset_func, \
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cortex_a9_core_pwr_dwn, \
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cortex_a9_cluster_pwr_dwn
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