mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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e6ef3ef0f6
This patch appends properties in DT bindings to differentiate between FVP and FPGA. The related macros are no longer used, so they are removed. This patch contains minor improvement for adding labels in device nodes. Change-Id: I8d708bb7a8a9a0ed32b806abcb4e7651daadf5e6 Signed-off-by: Leo Yan <leo.yan@arm.com>
65 lines
1.6 KiB
Text
65 lines
1.6 KiB
Text
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define GIC_CTRL_ADDR 2c010000
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#define GIC_GICR_OFFSET 0x200000
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#define UART_OFFSET 0x1000
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#define VENCODER_TIMING_CLK 25175000
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#define VENCODER_TIMING \
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clock-frequency = <VENCODER_TIMING_CLK>; \
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hactive = <640>; \
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vactive = <480>; \
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hfront-porch = <16>; \
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hback-porch = <48>; \
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hsync-len = <96>; \
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vfront-porch = <10>; \
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vback-porch = <33>; \
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vsync-len = <2>
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/ {
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chosen {
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stdout-path = "serial0:115200n8";
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};
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ethernet: ethernet@18000000 {
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compatible = "smsc,lan91c111";
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};
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mmci: mmci@1c050000 {
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cd-gpios = <&sysreg 0 0>;
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};
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rtc@1c170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x0 0x1C170000 0x0 0x1000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_refclk>;
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clock-names = "apb_pclk";
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};
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kmi@1c060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c060000 0x0 0x1000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c070000 0x0 0x1000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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virtio_block@1c130000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c130000 0x0 0x200>;
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/* spec lists this wrong */
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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