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47147013b4
Fix some typos and misspellings in TF-A documentation. Signed-off-by: David Horstmann <david.horstmann@arm.com> Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa
52 lines
1.5 KiB
ReStructuredText
52 lines
1.5 KiB
ReStructuredText
Marvell IOB address decoding bindings
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=====================================
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IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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The IOB includes a description of the address decoding configuration.
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IOB supports up to n (in CP110 n=24) windows for external memory transaction.
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When a transaction passes through the IOB, its address is compared to each of
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the enabled windows. If there is a hit and it passes the security checks, it is
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advanced to the target port.
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Mandatory functions
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-------------------
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- marvell_get_iob_memory_map
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Returns the IOB windows configuration and the number of windows
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Mandatory structures
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--------------------
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- iob_memory_map
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Array that includes the configuration of the windows. Every window/entry is
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a struct which has 3 parameters:
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- Base address of the window
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- Size of the window
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- Target-ID of the window
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Target ID options
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-----------------
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- **0x0** = Internal configuration space
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- **0x1** = MCI0
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- **0x2** = PEX1_X1
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- **0x3** = PEX2_X1
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- **0x4** = PEX0_X4
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- **0x5** = NAND flash
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- **0x6** = RUNIT (NOR/SPI/BootRoom)
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- **0x7** = MCI1
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Example
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-------
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.. code:: c
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struct addr_map_win iob_memory_map[] = {
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{0x00000000f7000000, 0x0000000001000000, PEX1_TID}, /* PEX1_X1 window */
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{0x00000000f8000000, 0x0000000001000000, PEX2_TID}, /* PEX2_X1 window */
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{0x00000000f6000000, 0x0000000001000000, PEX0_TID}, /* PEX0_X4 window */
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{0x00000000f9000000, 0x0000000001000000, NAND_TID} /* NAND window */
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};
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