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https://github.com/ARM-software/arm-trusted-firmware.git
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c71793c647
Add the dram retention flow for i.MX8M SoC family. Change-Id: Ifb8ba5b2f6f002133cf47c07fef73df29c51c890 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
72 lines
1.6 KiB
C
72 lines
1.6 KiB
C
/*
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* Copyright 2019-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <dram.h>
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struct dram_info dram_info;
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/* Restore the ddrc configs */
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void dram_umctl2_init(struct dram_timing_info *timing)
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{
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struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg;
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unsigned int i;
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for (i = 0U; i < timing->ddrc_cfg_num; i++) {
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mmio_write_32(ddrc_cfg->reg, ddrc_cfg->val);
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ddrc_cfg++;
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}
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/* set the default fsp to P0 */
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mmio_write_32(DDRC_MSTR2(0), 0x0);
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}
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/* Restore the dram PHY config */
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void dram_phy_init(struct dram_timing_info *timing)
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{
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struct dram_cfg_param *cfg = timing->ddrphy_cfg;
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unsigned int i;
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/* Restore the PHY init config */
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cfg = timing->ddrphy_cfg;
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for (i = 0U; i < timing->ddrphy_cfg_num; i++) {
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dwc_ddrphy_apb_wr(cfg->reg, cfg->val);
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cfg++;
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}
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/* Restore the DDR PHY CSRs */
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cfg = timing->ddrphy_trained_csr;
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for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) {
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dwc_ddrphy_apb_wr(cfg->reg, cfg->val);
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cfg++;
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}
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/* Load the PIE image */
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cfg = timing->ddrphy_pie;
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for (i = 0U; i < timing->ddrphy_pie_num; i++) {
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dwc_ddrphy_apb_wr(cfg->reg, cfg->val);
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cfg++;
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}
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}
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void dram_info_init(unsigned long dram_timing_base)
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{
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uint32_t ddrc_mstr, current_fsp;
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/* Get the dram type & rank */
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ddrc_mstr = mmio_read_32(DDRC_MSTR(0));
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dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK;
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dram_info.num_rank = (ddrc_mstr >> 24) & ACTIVE_RANK_MASK;
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/* Get current fsp info */
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current_fsp = mmio_read_32(DDRC_DFIMISC(0)) & 0xf;
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dram_info.boot_fsp = current_fsp;
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dram_info.current_fsp = current_fsp;
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dram_info.timing_info = (struct dram_timing_info *)dram_timing_base;
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}
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