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1fe4a9d181
Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
38 lines
1.5 KiB
C
38 lines
1.5 KiB
C
/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_V1_H
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#define NEOVERSE_V1_H
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#define NEOVERSE_V1_MIDR U(0x410FD400)
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/* Neoverse V1 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_V1_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
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#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
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#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
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#define CPUECTLR_EL1_PF_MODE_LSB U(6)
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#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
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#endif /* NEOVERSE_V1_H */
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