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1fe4a9d181
Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
43 lines
1.6 KiB
C
43 lines
1.6 KiB
C
/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A77_H
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#define CORTEX_A77_H
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#include <lib/utils_def.h>
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/* Cortex-A77 MIDR */
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#define CORTEX_A77_MIDR U(0x410FD0D0)
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/* Cortex-A77 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A77_BHB_LOOP_COUNT U(24)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
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/*******************************************************************************
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* CPU Power Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
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#define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3
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#define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4
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#define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5
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#endif /* CORTEX_A77_H */
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