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1fe4a9d181
Implements the loop workaround for Cortex-A77, Cortex-A78, Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1 CPUs. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
54 lines
2.4 KiB
C
54 lines
2.4 KiB
C
/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A710_H
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#define CORTEX_A710_H
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#define CORTEX_A710_MIDR U(0x410FD470)
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/* Cortex-A710 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A710_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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#define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
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#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
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#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
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#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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#endif /* CORTEX_A710_H */
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