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727bbf680d
As secondary cores show up, they populate an array to announce themselves so plat_core_pos_by_mpidr() can return an invalid COREID code for any non-existing MPIDR that it is queried about. The Power Domain Tree Description is populated with a topology based on the maximum harcoded values. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/utils_def.h>
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#ifndef FPGA_DEF_H
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#define FPGA_DEF_H
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/*
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* These are set to large values to account for images describing systems with
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* larger cluster configurations.
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*
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* For cases where the number of clusters, cores or threads is smaller than a
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* maximum value below, this does not affect the PSCI functionality as any PEs
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* that are present will still be indexed appropriately regardless of any empty
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* entries in the array used to represent the topology.
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*/
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#define FPGA_MAX_CLUSTER_COUNT 4
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#define FPGA_MAX_CPUS_PER_CLUSTER 8
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#define FPGA_MAX_PE_PER_CPU 4
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#define FPGA_PRIMARY_CPU 0x0
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/*******************************************************************************
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* FPGA image memory map related constants
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******************************************************************************/
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/*
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* UART base address, just for the crash console, as a fallback.
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* The actual console UART address is taken from the DT.
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*/
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#define PLAT_FPGA_CRASH_UART_BASE 0x7ff80000
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#define FPGA_DEFAULT_TIMER_FREQUENCY 10000000
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#endif
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