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1ea63d77a1
On ARM CSS platforms, the SCP_BL2/2U image is loaded below BL1 read-write data. This same memory is used to load BL31 later on. But sufficient checks were not done to ensure that the SCP_BL2 would not overwrite BL1 rw data. This patch adds the required CASSERT checks to prevent overwrite into BL1 or BL2 memory by load of SCP_BL2/2U. Also the size of BL31 is increased and SCP_BL2/2U size is decreased to accomodate it within the allocated region. Change-Id: I23b28b5e1589e91150852a06452bd52b273216ee Signed-off-by: Soby Mathew <soby.mathew@arm.com>
169 lines
5 KiB
C
169 lines
5 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CSS_DEF_H__
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#define __CSS_DEF_H__
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#include <arm_def.h>
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#include <tzc400.h>
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/*************************************************************************
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* Definitions common to all ARM Compute SubSystems (CSS)
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*************************************************************************/
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#define NSROM_BASE 0x1f000000
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#define NSROM_SIZE 0x00001000
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/* Following covers CSS Peripherals excluding NSROM and NSRAM */
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#define CSS_DEVICE_BASE 0x20000000
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#define CSS_DEVICE_SIZE 0x0e000000
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x00008000
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/* System Security Control Registers */
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#define SSC_REG_BASE 0x2a420000
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#define SSC_GPRETN (SSC_REG_BASE + 0x030)
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/* The slave_bootsecure controls access to GPU, DMC and CS. */
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#define CSS_NIC400_SLAVE_BOOTSECURE 8
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/* Interrupt handling constants */
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#define CSS_IRQ_MHU 69
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#define CSS_IRQ_GPU_SMMU_0 71
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#define CSS_IRQ_TZC 80
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#define CSS_IRQ_TZ_WDOG 86
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#define CSS_IRQ_SEC_SYS_TIMER 91
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/*
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* Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a
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* GICv2 system or mode, the interrupts will be treated as Group 0 interrupts.
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*/
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#define CSS_G1S_IRQS CSS_IRQ_MHU, \
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CSS_IRQ_GPU_SMMU_0, \
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CSS_IRQ_TZC, \
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CSS_IRQ_TZ_WDOG, \
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CSS_IRQ_SEC_SYS_TIMER
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/*
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* The lower Non-secure MHU channel is being used for SCMI for ARM Trusted
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* Firmware.
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* TODO: Move SCMI to Secure channel once the migration to SCMI in SCP is
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* complete.
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*/
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#define MHU_CPU_INTR_L_SET_OFFSET 0x108
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#define MHU_CPU_INTR_H_SET_OFFSET 0x128
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#define CSS_SCMI_PAYLOAD_BASE (NSRAM_BASE + 0x500)
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#define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_L_SET_OFFSET
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/*
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* SCP <=> AP boot configuration
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*
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* The SCP/AP boot configuration is a 32-bit word located at a known offset from
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* the start of the Trusted SRAM.
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*
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* Note that the value stored at this address is only valid at boot time, before
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* the SCP_BL2 image is transferred to SCP.
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*/
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#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE
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#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
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CSS_DEVICE_BASE, \
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CSS_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define CSS_MAP_NSRAM MAP_REGION_FLAT( \
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NSRAM_BASE, \
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NSRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* Platform ID address */
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#define SSC_VERSION_OFFSET 0x040
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#define SSC_VERSION_CONFIG_SHIFT 28
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#define SSC_VERSION_MAJOR_REV_SHIFT 24
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#define SSC_VERSION_MINOR_REV_SHIFT 20
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#define SSC_VERSION_DESIGNER_ID_SHIFT 12
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#define SSC_VERSION_PART_NUM_SHIFT 0x0
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#define SSC_VERSION_CONFIG_MASK 0xf
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#define SSC_VERSION_MAJOR_REV_MASK 0xf
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#define SSC_VERSION_MINOR_REV_MASK 0xf
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#define SSC_VERSION_DESIGNER_ID_MASK 0xff
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#define SSC_VERSION_PART_NUM_MASK 0xfff
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/* SSC debug configuration registers */
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#define SSC_DBGCFG_SET 0x14
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#define SSC_DBGCFG_CLR 0x18
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#define SPIDEN_INT_CLR_SHIFT 6
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#define SPIDEN_SEL_SET_SHIFT 7
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#ifndef __ASSEMBLY__
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/* SSC_VERSION related accessors */
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/* Returns the part number of the platform */
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#define GET_SSC_VERSION_PART_NUM(val) \
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(((val) >> SSC_VERSION_PART_NUM_SHIFT) & \
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SSC_VERSION_PART_NUM_MASK)
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/* Returns the configuration number of the platform */
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#define GET_SSC_VERSION_CONFIG(val) \
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(((val) >> SSC_VERSION_CONFIG_SHIFT) & \
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SSC_VERSION_CONFIG_MASK)
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#endif /* __ASSEMBLY__ */
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/*************************************************************************
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* Required platform porting definitions common to all
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* ARM Compute SubSystems (CSS)
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************************************************************************/
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/*
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* The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there
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* respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE).
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* Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load
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* an SCP_BL2/SCP_BL2U image.
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*/
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#if CSS_LOAD_SCP_IMAGES
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#if ARM_BL31_IN_DRAM
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#error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config"
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#endif
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/*
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* Load address of SCP_BL2 in CSS platform ports
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* SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1
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* rw data. Once SCP_BL2 is transferred to the SCP, it is discarded and BL31
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* is loaded over the top.
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*/
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#define SCP_BL2_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE)
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#define SCP_BL2_LIMIT BL1_RW_BASE
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#define SCP_BL2U_BASE (BL1_RW_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE)
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#define SCP_BL2U_LIMIT BL1_RW_BASE
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#endif /* CSS_LOAD_SCP_IMAGES */
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/* Load address of Non-Secure Image for CSS platform ports */
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#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000
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/* TZC related constants */
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#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
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/* Trusted mailbox base address common to all CSS */
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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/*
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* Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP
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* command
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*/
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#define CSS_CLUSTER_PWR_STATE_ON 0
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#define CSS_CLUSTER_PWR_STATE_OFF 3
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#define CSS_CPU_PWR_STATE_ON 1
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#define CSS_CPU_PWR_STATE_OFF 0
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#define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1)
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#endif /* __CSS_DEF_H__ */
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