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https://github.com/ARM-software/arm-trusted-firmware.git
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This patch updates and refactors the GPT library and fixes bugs. - Support all combinations of PGS, PPS, and L0GPTSZ parameters. - PPS and PGS are set at runtime, L0GPTSZ is read from GPCCR_EL3. - Use compiler definitions to simplify code. - Renaming functions to better suit intended uses. - MMU enabled before GPT APIs called. - Add comments to make function usage more clear in GPT library. - Added _rme suffix to file names to differentiate better from the GPT file system code. - Renamed gpt_defs.h to gpt_rme_private.h to better separate private and public code. - Renamed gpt_core.c to gpt_rme.c to better conform to TF-A precedent. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I4cbb23b0f81e697baa9fb23ba458aa3f7d1ed919
345 lines
10 KiB
C
345 lines
10 KiB
C
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <arch_features.h>
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#include <bl31/bl31.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <context.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/gpt_rme/gpt_rme.h>
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#include <lib/spinlock.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/common_def.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <services/gtsi_svc.h>
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#include <services/rmi_svc.h>
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#include <services/rmmd_svc.h>
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#include <smccc_helpers.h>
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#include "rmmd_initial_context.h"
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#include "rmmd_private.h"
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/*******************************************************************************
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* RMM context information.
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******************************************************************************/
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rmmd_rmm_context_t rmm_context[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* RMM entry point information. Discovered on the primary core and reused
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* on secondary cores.
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******************************************************************************/
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static entry_point_info_t *rmm_ep_info;
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/*******************************************************************************
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* Static function declaration.
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******************************************************************************/
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static int32_t rmm_init(void);
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static uint64_t rmmd_smc_forward(uint32_t smc_fid, uint32_t src_sec_state,
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uint32_t dst_sec_state, uint64_t x1,
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uint64_t x2, uint64_t x3, uint64_t x4,
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void *handle);
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/*******************************************************************************
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* This function takes an RMM context pointer and performs a synchronous entry
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* into it.
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******************************************************************************/
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uint64_t rmmd_rmm_sync_entry(rmmd_rmm_context_t *rmm_ctx)
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{
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uint64_t rc;
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assert(rmm_ctx != NULL);
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cm_set_context(&(rmm_ctx->cpu_ctx), REALM);
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/* Save the current el1/el2 context before loading realm context. */
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cm_el1_sysregs_context_save(NON_SECURE);
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cm_el2_sysregs_context_save(NON_SECURE);
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/* Restore the realm context assigned above */
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cm_el1_sysregs_context_restore(REALM);
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cm_el2_sysregs_context_restore(REALM);
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cm_set_next_eret_context(REALM);
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/* Enter RMM */
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rc = rmmd_rmm_enter(&rmm_ctx->c_rt_ctx);
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/* Save realm context */
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cm_el1_sysregs_context_save(REALM);
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cm_el2_sysregs_context_save(REALM);
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/* Restore the el1/el2 context again. */
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cm_el1_sysregs_context_restore(NON_SECURE);
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cm_el2_sysregs_context_restore(NON_SECURE);
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return rc;
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}
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/*******************************************************************************
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* This function returns to the place where rmmd_rmm_sync_entry() was
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* called originally.
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******************************************************************************/
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__dead2 void rmmd_rmm_sync_exit(uint64_t rc)
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{
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rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()];
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/* Get context of the RMM in use by this CPU. */
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assert(cm_get_context(REALM) == &(ctx->cpu_ctx));
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/*
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* The RMMD must have initiated the original request through a
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* synchronous entry into RMM. Jump back to the original C runtime
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* context with the value of rc in x0;
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*/
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rmmd_rmm_exit(ctx->c_rt_ctx, rc);
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panic();
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}
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static void rmm_el2_context_init(el2_sysregs_t *regs)
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{
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regs->ctx_regs[CTX_SPSR_EL2 >> 3] = REALM_SPSR_EL2;
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regs->ctx_regs[CTX_SCTLR_EL2 >> 3] = SCTLR_EL2_RES1;
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}
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/*******************************************************************************
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* Jump to the RMM for the first time.
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******************************************************************************/
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static int32_t rmm_init(void)
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{
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uint64_t rc;
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rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()];
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INFO("RMM init start.\n");
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ctx->state = RMM_STATE_RESET;
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/* Initialize RMM EL2 context. */
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rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx);
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rc = rmmd_rmm_sync_entry(ctx);
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if (rc != 0ULL) {
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ERROR("RMM initialisation failed 0x%llx\n", rc);
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panic();
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}
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ctx->state = RMM_STATE_IDLE;
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INFO("RMM init end.\n");
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return 1;
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}
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/*******************************************************************************
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* Load and read RMM manifest, setup RMM.
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******************************************************************************/
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int rmmd_setup(void)
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{
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uint32_t ep_attr;
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unsigned int linear_id = plat_my_core_pos();
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rmmd_rmm_context_t *rmm_ctx = &rmm_context[linear_id];
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/* Make sure RME is supported. */
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assert(get_armv9_2_feat_rme_support() != 0U);
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rmm_ep_info = bl31_plat_get_next_image_ep_info(REALM);
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if (rmm_ep_info == NULL) {
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WARN("No RMM image provided by BL2 boot loader, Booting "
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"device without RMM initialization. SMCs destined for "
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"RMM will return SMC_UNK\n");
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return -ENOENT;
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}
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/* Under no circumstances will this parameter be 0 */
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assert(rmm_ep_info->pc == RMM_BASE);
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/* Initialise an entrypoint to set up the CPU context */
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ep_attr = EP_REALM;
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if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0U) {
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ep_attr |= EP_EE_BIG;
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}
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SET_PARAM_HEAD(rmm_ep_info, PARAM_EP, VERSION_1, ep_attr);
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rmm_ep_info->spsr = SPSR_64(MODE_EL2,
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MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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/* Initialise RMM context with this entry point information */
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cm_setup_context(&rmm_ctx->cpu_ctx, rmm_ep_info);
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INFO("RMM setup done.\n");
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/* Register init function for deferred init. */
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bl31_register_rmm_init(&rmm_init);
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return 0;
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}
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/*******************************************************************************
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* Forward SMC to the other security state
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******************************************************************************/
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static uint64_t rmmd_smc_forward(uint32_t smc_fid, uint32_t src_sec_state,
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uint32_t dst_sec_state, uint64_t x1,
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uint64_t x2, uint64_t x3, uint64_t x4,
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void *handle)
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{
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/* Save incoming security state */
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cm_el1_sysregs_context_save(src_sec_state);
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cm_el2_sysregs_context_save(src_sec_state);
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/* Restore outgoing security state */
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cm_el1_sysregs_context_restore(dst_sec_state);
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cm_el2_sysregs_context_restore(dst_sec_state);
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cm_set_next_eret_context(dst_sec_state);
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SMC_RET8(cm_get_context(dst_sec_state), smc_fid, x1, x2, x3, x4,
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SMC_GET_GP(handle, CTX_GPREG_X5),
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SMC_GET_GP(handle, CTX_GPREG_X6),
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SMC_GET_GP(handle, CTX_GPREG_X7));
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}
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/*******************************************************************************
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* This function handles all SMCs in the range reserved for RMI. Each call is
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* either forwarded to the other security state or handled by the RMM dispatcher
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******************************************************************************/
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uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
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uint64_t x3, uint64_t x4, void *cookie,
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void *handle, uint64_t flags)
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{
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rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()];
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uint32_t src_sec_state;
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/* Determine which security state this SMC originated from */
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src_sec_state = caller_sec_state(flags);
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/* RMI must not be invoked by the Secure world */
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if (src_sec_state == SMC_FROM_SECURE) {
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WARN("RMM: RMI invoked by secure world.\n");
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SMC_RET1(handle, SMC_UNK);
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}
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/*
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* Forward an RMI call from the Normal world to the Realm world as it
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* is.
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*/
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if (src_sec_state == SMC_FROM_NON_SECURE) {
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VERBOSE("RMM: RMI call from non-secure world.\n");
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return rmmd_smc_forward(smc_fid, NON_SECURE, REALM,
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x1, x2, x3, x4, handle);
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}
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assert(src_sec_state == SMC_FROM_REALM);
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switch (smc_fid) {
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case RMI_RMM_REQ_COMPLETE:
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if (ctx->state == RMM_STATE_RESET) {
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VERBOSE("RMM: running rmmd_rmm_sync_exit\n");
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rmmd_rmm_sync_exit(x1);
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}
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return rmmd_smc_forward(x1, REALM, NON_SECURE,
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x2, x3, x4, 0, handle);
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default:
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WARN("RMM: Unsupported RMM call 0x%08x\n", smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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}
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/*******************************************************************************
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* This cpu has been turned on. Enter RMM to initialise R-EL2. Entry into RMM
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* is done after initialising minimal architectural state that guarantees safe
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* execution.
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******************************************************************************/
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static void *rmmd_cpu_on_finish_handler(const void *arg)
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{
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int32_t rc;
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uint32_t linear_id = plat_my_core_pos();
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rmmd_rmm_context_t *ctx = &rmm_context[linear_id];
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ctx->state = RMM_STATE_RESET;
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/* Initialise RMM context with this entry point information */
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cm_setup_context(&ctx->cpu_ctx, rmm_ep_info);
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/* Initialize RMM EL2 context. */
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rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx);
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rc = rmmd_rmm_sync_entry(ctx);
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if (rc != 0) {
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ERROR("RMM initialisation failed (%d) on CPU%d\n", rc,
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linear_id);
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panic();
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}
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ctx->state = RMM_STATE_IDLE;
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return NULL;
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}
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/* Subscribe to PSCI CPU on to initialize RMM on secondary */
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SUBSCRIBE_TO_EVENT(psci_cpu_on_finish, rmmd_cpu_on_finish_handler);
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static int gtsi_transition_granule(uint64_t pa,
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unsigned int src_sec_state,
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unsigned int target_pas)
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{
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int ret;
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ret = gpt_transition_pas(pa, PAGE_SIZE_4KB, src_sec_state, target_pas);
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/* Convert TF-A error codes into GTSI error codes */
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if (ret == -EINVAL) {
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ERROR("[GTSI] Transition failed: invalid %s\n", "address");
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ERROR(" PA: 0x%llx, SRC: %d, PAS: %d\n", pa,
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src_sec_state, target_pas);
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ret = GRAN_TRANS_RET_BAD_ADDR;
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} else if (ret == -EPERM) {
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ERROR("[GTSI] Transition failed: invalid %s\n", "caller/PAS");
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ERROR(" PA: 0x%llx, SRC: %d, PAS: %d\n", pa,
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src_sec_state, target_pas);
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ret = GRAN_TRANS_RET_BAD_PAS;
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}
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return ret;
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}
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/*******************************************************************************
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* This function handles all SMCs in the range reserved for GTF.
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******************************************************************************/
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uint64_t rmmd_gtsi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
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uint64_t x3, uint64_t x4, void *cookie,
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void *handle, uint64_t flags)
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{
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uint32_t src_sec_state;
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/* Determine which security state this SMC originated from */
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src_sec_state = caller_sec_state(flags);
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if (src_sec_state != SMC_FROM_REALM) {
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WARN("RMM: GTF call originated from secure or normal world\n");
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SMC_RET1(handle, SMC_UNK);
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}
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switch (smc_fid) {
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case SMC_ASC_MARK_REALM:
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SMC_RET1(handle, gtsi_transition_granule(x1, SMC_FROM_REALM,
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GPT_GPI_REALM));
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case SMC_ASC_MARK_NONSECURE:
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SMC_RET1(handle, gtsi_transition_granule(x1, SMC_FROM_REALM,
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GPT_GPI_NS));
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default:
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WARN("RMM: Unsupported GTF call 0x%08x\n", smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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}
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