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https://github.com/ARM-software/arm-trusted-firmware.git
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d22f1d3587
VERBOSE print logs need a larger stack size and the currently configured BL2 stack size was insufficient for FVP. This patch increases the same. Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I316ba2ea467571161b5f4807e6e5fa0bf89d44c6
344 lines
10 KiB
C
344 lines
10 KiB
C
/*
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* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <drivers/arm/tzc400.h>
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#include <lib/utils_def.h>
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/common/arm_spm_def.h>
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#include <plat/common/common_def.h>
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#include "../fvp_def.h"
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/* Required platform porting definitions */
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#define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \
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U(FVP_MAX_CPUS_PER_CLUSTER) * \
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U(FVP_MAX_PE_PER_CPU))
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#define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \
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PLATFORM_CORE_COUNT + U(1))
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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/*
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* Other platform porting definitions are provided by included headers
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*/
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/*
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* Required ARM standard platform porting definitions
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*/
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#define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT)
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#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */
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#define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000)
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#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */
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#define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000)
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#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
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#if ENABLE_RME
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#define PLAT_ARM_RMM_BASE (RMM_BASE)
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#define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE)
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#endif
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/*
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* Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to
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* max size of BL32 image.
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*/
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#if defined(SPD_spmd)
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#define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE
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#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
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#endif
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/* virtual address used by dynamic mem_protect for chunk_base */
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#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
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/* No SCP in FVP */
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
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#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
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#define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
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/* Range of kernel DTB load address */
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#define FVP_DTB_DRAM_MAP_START ULL(0x82000000)
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#define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */
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#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
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FVP_DTB_DRAM_MAP_START, \
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FVP_DTB_DRAM_MAP_SIZE, \
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MT_MEMORY | MT_RO | MT_NS)
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/*
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* Load address of BL33 for this platform port
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*/
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#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000))
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#if defined(IMAGE_BL31)
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# if SPM_MM
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# define PLAT_ARM_MMAP_ENTRIES 10
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# if ENABLE_RME
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# define MAX_XLAT_TABLES 10
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# else
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# define MAX_XLAT_TABLES 9
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# endif
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# define PLAT_SP_IMAGE_MMAP_REGIONS 30
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
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# else
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# define PLAT_ARM_MMAP_ENTRIES 9
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# if USE_DEBUGFS
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# if ENABLE_RME
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# define MAX_XLAT_TABLES 9
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# else
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# define MAX_XLAT_TABLES 8
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# endif
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# else
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# if ENABLE_RME
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# define MAX_XLAT_TABLES 8
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# else
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# define MAX_XLAT_TABLES 7
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# endif
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# endif
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# endif
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#elif defined(IMAGE_BL32)
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# define PLAT_ARM_MMAP_ENTRIES 9
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# define MAX_XLAT_TABLES 6
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#elif !USE_ROMLIB
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# define PLAT_ARM_MMAP_ENTRIES 11
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# define MAX_XLAT_TABLES 5
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#else
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# define PLAT_ARM_MMAP_ENTRIES 12
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# define MAX_XLAT_TABLES 6
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#endif
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
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/*
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* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
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*/
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#if USE_ROMLIB
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
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#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000)
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#else
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
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#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0)
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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#if COT_DESC_IN_DTB
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# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION)
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#else
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# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION)
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#endif
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#else
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# define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION)
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#endif
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#if RESET_TO_BL31
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/* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */
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#define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
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ARM_SHARED_RAM_SIZE - \
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ARM_L0_GPT_SIZE)
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#else
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/*
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
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* calculated using the current BL31 PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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*/
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#define PLAT_ARM_MAX_BL31_SIZE (UL(0x3D000) - ARM_L0_GPT_SIZE)
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#endif /* RESET_TO_BL31 */
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#ifndef __aarch64__
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#if RESET_TO_SP_MIN
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/* Size of Trusted SRAM - the first 4KB of shared memory */
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#define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
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ARM_SHARED_RAM_SIZE)
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#else
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/*
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* Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
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* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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*/
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# define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000)
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#endif /* RESET_TO_SP_MIN */
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#endif
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/*
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* Size of cacheable stacks
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*/
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#if defined(IMAGE_BL1)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE UL(0x1000)
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# else
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# define PLATFORM_STACK_SIZE UL(0x500)
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# endif
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#elif defined(IMAGE_BL2)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE UL(0x1000)
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# else
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# define PLATFORM_STACK_SIZE UL(0x600)
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# endif
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#elif defined(IMAGE_BL2U)
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# define PLATFORM_STACK_SIZE UL(0x400)
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#elif defined(IMAGE_BL31)
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# define PLATFORM_STACK_SIZE UL(0x800)
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE UL(0x440)
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#elif defined(IMAGE_RMM)
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# define PLATFORM_STACK_SIZE UL(0x440)
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#endif
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/* Reserve the last block of flash for PSCI MEM PROTECT flag */
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#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#if ARM_GPT_SUPPORT
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/*
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* Offset of the FIP in the GPT image. BL1 component uses this option
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* as it does not load the partition table to get the FIP base
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* address. At sector 34 by default (i.e. after reserved sectors 0-33)
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* Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
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*/
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#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400
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#endif /* ARM_GPT_SUPPORT */
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/*
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* PL011 related constants
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*/
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#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
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#define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
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#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
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#define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE
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#define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ
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#define PLAT_FVP_SMMUV3_BASE UL(0x2b400000)
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/* CCI related constants */
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#define PLAT_FVP_CCI400_BASE UL(0x2c090000)
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#define PLAT_FVP_CCI400_CLUS0_SL_PORT 3
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#define PLAT_FVP_CCI400_CLUS1_SL_PORT 4
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/* CCI-500/CCI-550 on Base platform */
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#define PLAT_FVP_CCI5XX_BASE UL(0x2a000000)
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#define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5
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#define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6
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/* CCN related constants. Only CCN 502 is currently supported */
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#define PLAT_ARM_CCN_BASE UL(0x2e000000)
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#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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/* Mailbox base address */
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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/* TrustZone controller related constants
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*
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* Currently only filters 0 and 2 are connected on Base FVP.
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* Filter 0 : CPU clusters (no access to DRAM by default)
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* Filter 1 : not connected
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* Filter 2 : LCDs (access to VRAM allowed by default)
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* Filter 3 : not connected
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* Programming unconnected filters will have no effect at the
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* moment. These filter could, however, be connected in future.
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* So care should be taken not to configure the unused filters.
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*
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* Allow only non-secure access to all DRAM to supported devices.
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* Give access to the CPUs and Virtio. Some devices
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* would normally use the default ID so allow that too.
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*/
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#define PLAT_ARM_TZC_BASE UL(0x2a4a0000)
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#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
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#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD))
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/*
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* GIC related constants to cater for both GICv2 and GICv3 instances of an
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* FVP. They could be overridden at runtime in case the FVP implements the
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* legacy VE memory map.
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*/
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#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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#define PLAT_ARM_GICR_BASE BASE_GICR_BASE
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#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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ARM_G1S_IRQ_PROPS(grp), \
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INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#if SDEI_IN_FCONF
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#define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT
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#define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT
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#else
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#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
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#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
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#endif
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
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PLAT_SP_IMAGE_NS_BUF_SIZE)
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#define PLAT_SP_PRI PLAT_RAS_PRI
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/*
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* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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#endif /* PLATFORM_DEF_H */
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