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f19dc624a1
This patch updates and refactors the GPT library and fixes bugs. - Support all combinations of PGS, PPS, and L0GPTSZ parameters. - PPS and PGS are set at runtime, L0GPTSZ is read from GPCCR_EL3. - Use compiler definitions to simplify code. - Renaming functions to better suit intended uses. - MMU enabled before GPT APIs called. - Add comments to make function usage more clear in GPT library. - Added _rme suffix to file names to differentiate better from the GPT file system code. - Renamed gpt_defs.h to gpt_rme_private.h to better separate private and public code. - Renamed gpt_core.c to gpt_rme.c to better conform to TF-A precedent. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I4cbb23b0f81e697baa9fb23ba458aa3f7d1ed919
228 lines
7.3 KiB
C
228 lines
7.3 KiB
C
/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GPT_RME_PRIVATE_H
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#define GPT_RME_PRIVATE_H
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#include <arch.h>
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#include <lib/gpt_rme/gpt_rme.h>
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#include <lib/utils_def.h>
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/******************************************************************************/
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/* GPT descriptor definitions */
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/******************************************************************************/
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/* GPT level 0 descriptor bit definitions. */
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#define GPT_L0_TYPE_MASK UL(0xF)
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#define GPT_L0_TYPE_SHIFT U(0)
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/* For now, we don't support contiguous descriptors, only table and block. */
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#define GPT_L0_TYPE_TBL_DESC UL(0x3)
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#define GPT_L0_TYPE_BLK_DESC UL(0x1)
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#define GPT_L0_TBL_DESC_L1ADDR_MASK UL(0xFFFFFFFFFF)
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#define GPT_L0_TBL_DESC_L1ADDR_SHIFT U(12)
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#define GPT_L0_BLK_DESC_GPI_MASK UL(0xF)
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#define GPT_L0_BLK_DESC_GPI_SHIFT U(4)
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/* GPT level 1 descriptor bit definitions */
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#define GPT_L1_GRAN_DESC_GPI_MASK UL(0xF)
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/*
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* This macro fills out every GPI entry in a granules descriptor to the same
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* value.
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*/
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#define GPT_BUILD_L1_DESC(_gpi) (((uint64_t)(_gpi) << 4*0) | \
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((uint64_t)(_gpi) << 4*1) | \
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((uint64_t)(_gpi) << 4*2) | \
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((uint64_t)(_gpi) << 4*3) | \
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((uint64_t)(_gpi) << 4*4) | \
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((uint64_t)(_gpi) << 4*5) | \
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((uint64_t)(_gpi) << 4*6) | \
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((uint64_t)(_gpi) << 4*7) | \
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((uint64_t)(_gpi) << 4*8) | \
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((uint64_t)(_gpi) << 4*9) | \
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((uint64_t)(_gpi) << 4*10) | \
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((uint64_t)(_gpi) << 4*11) | \
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((uint64_t)(_gpi) << 4*12) | \
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((uint64_t)(_gpi) << 4*13) | \
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((uint64_t)(_gpi) << 4*14) | \
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((uint64_t)(_gpi) << 4*15))
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/******************************************************************************/
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/* GPT platform configuration */
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/******************************************************************************/
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/* This value comes from GPCCR_EL3 so no externally supplied definition. */
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#define GPT_L0GPTSZ ((unsigned int)((read_gpccr_el3() >> \
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GPCCR_L0GPTSZ_SHIFT) & GPCCR_L0GPTSZ_MASK))
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/* The "S" value is directly related to L0GPTSZ */
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#define GPT_S_VAL (GPT_L0GPTSZ + 30U)
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/*
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* Map PPS values to T values.
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*
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* PPS Size T
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* 0b000 4GB 32
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* 0b001 64GB 36
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* 0b010 1TB 40
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* 0b011 4TB 42
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* 0b100 16TB 44
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* 0b101 256TB 48
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* 0b110 4PB 52
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*
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* See section 15.1.27 of the RME specification.
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*/
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typedef enum {
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PPS_4GB_T = 32U,
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PPS_64GB_T = 36U,
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PPS_1TB_T = 40U,
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PPS_4TB_T = 42U,
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PPS_16TB_T = 44U,
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PPS_256TB_T = 48U,
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PPS_4PB_T = 52U
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} gpt_t_val_e;
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/*
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* Map PGS values to P values.
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*
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* PGS Size P
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* 0b00 4KB 12
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* 0b10 16KB 14
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* 0b01 64KB 16
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*
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* Note that pgs=0b10 is 16KB and pgs=0b01 is 64KB, this is not a typo.
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*
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* See section 15.1.27 of the RME specification.
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*/
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typedef enum {
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PGS_4KB_P = 12U,
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PGS_16KB_P = 14U,
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PGS_64KB_P = 16U
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} gpt_p_val_e;
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/* Max valid value for PGS. */
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#define GPT_PGS_MAX (2U)
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/* Max valid value for PPS. */
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#define GPT_PPS_MAX (6U)
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/******************************************************************************/
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/* L0 address attribute macros */
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/******************************************************************************/
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/*
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* If S is greater than or equal to T then there is a single L0 region covering
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* the entire protected space so there is no L0 index, so the width (and the
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* derivative mask value) are both zero. If we don't specifically handle this
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* special case we'll get a negative width value which does not make sense and
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* could cause a lot of problems.
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*/
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#define GPT_L0_IDX_WIDTH(_t) (((_t) > GPT_S_VAL) ? \
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((_t) - GPT_S_VAL) : (0U))
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/* Bit shift for the L0 index field in a PA. */
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#define GPT_L0_IDX_SHIFT (GPT_S_VAL)
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/* Mask for the L0 index field, must be shifted. */
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#define GPT_L0_IDX_MASK(_t) (0xFFFFFFFFFFFFFFFFUL >> \
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(64U - (GPT_L0_IDX_WIDTH(_t))))
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/* Total number of L0 regions. */
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#define GPT_L0_REGION_COUNT(_t) ((GPT_L0_IDX_MASK(_t)) + 1U)
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/* Total size of each GPT L0 region in bytes. */
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#define GPT_L0_REGION_SIZE (1UL << (GPT_L0_IDX_SHIFT))
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/* Total size in bytes of the whole L0 table. */
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#define GPT_L0_TABLE_SIZE(_t) ((GPT_L0_REGION_COUNT(_t)) << 3U)
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/******************************************************************************/
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/* L1 address attribute macros */
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/******************************************************************************/
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/* Width of the L1 index field. */
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#define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - ((_p) + 3U))
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/* Bit shift for the L1 index field. */
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#define GPT_L1_IDX_SHIFT(_p) ((_p) + 4U)
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/* Mask for the L1 index field, must be shifted. */
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#define GPT_L1_IDX_MASK(_p) (0xFFFFFFFFFFFFFFFFUL >> \
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(64U - (GPT_L1_IDX_WIDTH(_p))))
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/* Bit shift for the index of the L1 GPI in a PA. */
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#define GPT_L1_GPI_IDX_SHIFT(_p) (_p)
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/* Mask for the index of the L1 GPI in a PA. */
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#define GPT_L1_GPI_IDX_MASK (0xF)
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/* Total number of entries in each L1 table. */
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#define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1U)
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/* Total size in bytes of each L1 table. */
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#define GPT_L1_TABLE_SIZE(_p) ((GPT_L1_ENTRY_COUNT(_p)) << 3U)
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/******************************************************************************/
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/* General helper macros */
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/******************************************************************************/
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/* Protected space actual size in bytes. */
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#define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (_t))
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/* Granule actual size in bytes. */
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#define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (_p))
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/* L0 GPT region size in bytes. */
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#define GPT_L0GPTSZ_ACTUAL_SIZE (1UL << GPT_S_VAL)
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/* Get the index of the L0 entry from a physical address. */
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#define GPT_L0_IDX(_pa) ((_pa) >> GPT_L0_IDX_SHIFT)
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/*
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* This definition is used to determine if a physical address lies on an L0
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* region boundary.
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*/
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#define GPT_IS_L0_ALIGNED(_pa) (((_pa) & (GPT_L0_REGION_SIZE - U(1))) == U(0))
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/* Get the type field from an L0 descriptor. */
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#define GPT_L0_TYPE(_desc) (((_desc) >> GPT_L0_TYPE_SHIFT) & \
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GPT_L0_TYPE_MASK)
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/* Create an L0 block descriptor. */
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#define GPT_L0_BLK_DESC(_gpi) (GPT_L0_TYPE_BLK_DESC | \
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(((_gpi) & GPT_L0_BLK_DESC_GPI_MASK) << \
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GPT_L0_BLK_DESC_GPI_SHIFT))
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/* Create an L0 table descriptor with an L1 table address. */
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#define GPT_L0_TBL_DESC(_pa) (GPT_L0_TYPE_TBL_DESC | ((uint64_t)(_pa) & \
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(GPT_L0_TBL_DESC_L1ADDR_MASK << \
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GPT_L0_TBL_DESC_L1ADDR_SHIFT)))
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/* Get the GPI from an L0 block descriptor. */
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#define GPT_L0_BLKD_GPI(_desc) (((_desc) >> GPT_L0_BLK_DESC_GPI_SHIFT) & \
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GPT_L0_BLK_DESC_GPI_MASK)
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/* Get the L1 address from an L0 table descriptor. */
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#define GPT_L0_TBLD_ADDR(_desc) ((uint64_t *)(((_desc) & \
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(GPT_L0_TBL_DESC_L1ADDR_MASK << \
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GPT_L0_TBL_DESC_L1ADDR_SHIFT))))
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/* Get the index into the L1 table from a physical address. */
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#define GPT_L1_IDX(_p, _pa) (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & \
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GPT_L1_IDX_MASK(_p))
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/* Get the index of the GPI within an L1 table entry from a physical address. */
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#define GPT_L1_GPI_IDX(_p, _pa) (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & \
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GPT_L1_GPI_IDX_MASK)
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/* Determine if an address is granule-aligned. */
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#define GPT_IS_L1_ALIGNED(_p, _pa) (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - U(1))) \
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== U(0))
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#endif /* GPT_RME_PRIVATE_H */
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