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https://github.com/ARM-software/arm-trusted-firmware.git
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fcd41e8692
Add the basic support for i.MX8ULP. The i.MX 8ULP family of processors features NXP’s advanced implementation of the dual Arm Cortex-A35 cores alongside an Arm Cortex-M33. This combined architecture enables the device to run a rich operating system (such as Linux) on the Cortex-A35 core and an RTOS (such as FreeRTOS) on the Cortex-M33 core. It also includes a Cadence Tensilica Fusion DSP for low-power audio and a HiFi4 DSP for advanced audio and machine learning applications. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* Copyright 2021-2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX8_SCMI_H
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#define IMX8_SCMI_H
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#include <stdint.h>
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#define SCMI_SHMEM_CHANNEL_ERROR BIT_32(1)
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#define SCMI_SHMEM_CHANNEL_FREE BIT_32(0)
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#define SCMI_SHMEM_FLAG_INTR_ENABLED BIT_32(0)
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enum scmi_std_protocol {
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SCMI_PROTOCOL_BASE = 0x10,
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SCMI_PROTOCOL_POWER_DOMAIN = 0x11,
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SCMI_PROTOCOL_SYS_POWER = 0x12,
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SCMI_PROTOCOL_PERF_DOMAIN = 0x13,
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SCMI_PROTOCOL_CLK = 0x14,
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SCMI_PROTOCOL_SENSOR = 0x15,
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SCMI_PROTOCOL_RESET_DOMAIN = 0x16,
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};
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#define MSG_ID(m) ((m) & 0xff)
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#define MSG_TYPE(m) (((m) >> 8) & 0x3)
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#define MSG_PRO_ID(m) (((m) >> 10) & 0xff)
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#define MSG_TOKEN(m) (((m) >> 18) & 0x3ff)
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enum {
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SCMI_POWER_DOMAIN_PROTOCOL = 0x11,
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SCMI_SYS_PWR_DOMAIN_PROTOCOL = 0x12,
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SCMI_PER_DOMAIN_PROTOCOL = 0x13,
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SCMI_CLK_DOMAIN_PROTOCOL = 0x14,
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SCMI_SENSOR_PROTOCOL = 0x15,
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};
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#define PROTOCOL_VERSION 0
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#define PROTOCOL_ATTRIBUTES 1
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#define PROTOCOL_MESSAGE_ATTRIBUTES 2
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#define BASE_DISCOVER_VENDOR 3
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#define BASE_DISCOVER_SUB_VENDOR 4
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#define BASE_DISCOVER_IMPLEMENTATION_VERSION 5
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#define BASE_DISCOVER_LIST_PROTOCOLS 6
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#define BASE_DISCOVER_AGENT 7
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#define BASE_NOTIFY_ERRORS 8
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#define BASE_SET_DEVICE_PERMISSIONS 9
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#define BASE_SET_PROTOCOL_PERMISSIONS 0xA
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#define BASE_RESET_AGENT_CONFIGURATION 0xB
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enum {
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SCMI_RET_SUCCESS = 0,
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SCMI_RET_NOT_SUPPORTED = -1,
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SCMI_RET_INVALID_PARAMETERS = -2,
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SCMI_RET_DENIED = -3,
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SCMI_RET_NOT_FOUND = -4,
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SCMI_RET_OUT_OF_RANGE = -5,
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SCMI_RET_BUSY = -6,
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SCMI_RET_COMMS_ERROR = -7,
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SCMI_RET_GENERIC_ERROR = -8,
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SCMI_RET_HARDWARE_ERROR = -9,
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SCMI_RET_PROTOCOL_ERROR = -10,
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};
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#define POWER_DOMAIN_ATTRIBUTES 3
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#define POWER_DOMAIN_SUPPORT_NOTIFICATION BIT(31)
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#define POWER_DOMAIN_SUPPORT_ASYNCHRONOUS BIT(30)
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#define POWER_DOMAIN_SUPPORT_SYNCHRONOUS BIT(29)
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#define POWER_STATE_SET 4
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#define POWER_STATE_GET 5
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#define POWER_STATE_NOTIFY 6
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#define POWER_STATE_CHANGE_REQUESTED_NOTIFY 7
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int scmi_power_domain_handler(uint32_t msg_id, void *shmem);
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#define PERFORMANCE_DOMAIN_ATTRIBUTES 3
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#define PERFORMANCE_DESCRIBE_LEVELS 4
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#define PERFORMANCE_LIMITS_SET 5
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#define PERFORMANCE_LIMITS_GET 6
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#define PERFORMANCE_LEVEL_SET 7
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#define PERFORMANCE_LEVEL_GET 8
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#define PERFORMANCE_NOTIFY_LIMITS 9
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#define PERFORMANCE_NOTIFY_LEVEL 0xA
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#define PERFORMANCE_DESCRIBE_FAST_CHANNEL 0xB
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int scmi_perf_domain_handler(uint32_t msg_id, void *shmem);
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#define SENSOR_DESCRIPTION_GET 0x003
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#define SENSOR_CONFIG_SET 0x004
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#define SENSOR_TRIP_POINT_SET 0x005
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#define SENSOR_READING_GET 0x006
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int scmi_sensor_handler(uint32_t msg_id, void *shmem);
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#define SMC_SHMEM_BASE 0x2201f000
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#endif /* IMX8_SCMI_H */
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