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7c5eedca4c
JR1, JR2 and JR3 are available for use by the non secure world. Setup the A35 core DID for these job rings. Signed-off-by: Varun Sethi <v.sethi@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: If64d4ce11ebff49a2405d8b561b344fcd7b2614f
18 lines
377 B
C
18 lines
377 B
C
/*
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* Copyright 2021-2024 NXP.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <imx8ulp_caam.h>
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void imx8ulp_caam_init(void)
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{
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/* config CAAM JRaMID set MID to Cortex A */
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mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
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mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
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mmio_write_32(CAAM_JR2MID, CAAM_NS_MID);
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mmio_write_32(CAAM_JR3MID, CAAM_NS_MID);
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}
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