mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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311 lines
11 KiB
C
311 lines
11 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARM_DEF_H__
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#define __ARM_DEF_H__
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#include <arch.h>
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#include <common_def.h>
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#include <platform_def.h>
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#include <tbbr_img_def.h>
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#include <xlat_tables.h>
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/******************************************************************************
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* Definitions common to all ARM standard platforms
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*****************************************************************************/
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define ARM_SYSTEM_COUNT 1
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#define ARM_CACHE_WRITEBACK_SHIFT 6
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/*
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* Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
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* power levels have a 1:1 mapping with the MPIDR affinity levels.
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*/
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#define ARM_PWR_LVL0 MPIDR_AFFLVL0
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#define ARM_PWR_LVL1 MPIDR_AFFLVL1
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#define ARM_PWR_LVL2 MPIDR_AFFLVL2
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/*
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* Macros for local power states in ARM platforms encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define ARM_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define ARM_LOCAL_STATE_RET 1
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/* Local power state for OFF/power-down. Valid for CPU and cluster power
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domains */
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#define ARM_LOCAL_STATE_OFF 2
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/* Memory location options for TSP */
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#define ARM_TRUSTED_SRAM_ID 0
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#define ARM_TRUSTED_DRAM_ID 1
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#define ARM_DRAM_ID 2
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/* The first 4KB of Trusted SRAM are used as shared memory */
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#define ARM_TRUSTED_SRAM_BASE 0x04000000
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#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
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#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */
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/* The remaining Trusted SRAM is used to load the BL images */
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#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
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ARM_SHARED_RAM_SIZE)
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#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
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ARM_SHARED_RAM_SIZE)
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/*
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* The top 16MB of DRAM1 is configured as secure access only using the TZC
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* - SCP TZC DRAM: If present, DRAM reserved for SCP use
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* - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
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*/
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#define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000)
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#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - \
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ARM_SCP_TZC_DRAM1_SIZE)
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#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
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#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
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ARM_SCP_TZC_DRAM1_SIZE - 1)
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#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - \
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ARM_TZC_DRAM1_SIZE)
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#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
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ARM_SCP_TZC_DRAM1_SIZE)
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#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE - 1)
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#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
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#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
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ARM_TZC_DRAM1_SIZE)
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#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
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ARM_NS_DRAM1_SIZE - 1)
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#define ARM_DRAM1_BASE MAKE_ULL(0x80000000)
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#define ARM_DRAM1_SIZE MAKE_ULL(0x80000000)
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#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - 1)
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#define ARM_DRAM2_BASE MAKE_ULL(0x880000000)
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#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
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#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
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ARM_DRAM2_SIZE - 1)
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
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ARM_IRQ_SEC_SGI_1, \
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ARM_IRQ_SEC_SGI_2, \
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ARM_IRQ_SEC_SGI_3, \
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ARM_IRQ_SEC_SGI_4, \
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ARM_IRQ_SEC_SGI_5, \
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ARM_IRQ_SEC_SGI_7
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#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \
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ARM_IRQ_SEC_SGI_6
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#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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ARM_SHARED_RAM_BASE, \
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ARM_SHARED_RAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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ARM_NS_DRAM1_BASE, \
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ARM_NS_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
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TSP_SEC_MEM_BASE, \
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TSP_SEC_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* The number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU.
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*/
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#if USE_COHERENT_MEM
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#define ARM_BL_REGIONS 3
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#else
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#define ARM_BL_REGIONS 2
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#endif
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#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
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ARM_BL_REGIONS)
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/* Memory mapped Generic timer interfaces */
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#define ARM_SYS_CNTCTL_BASE 0x2a430000
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#define ARM_SYS_CNTREAD_BASE 0x2a800000
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#define ARM_SYS_TIMCTL_BASE 0x2a810000
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#define ARM_CONSOLE_BAUDRATE 115200
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/* Trusted Watchdog constants */
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#define ARM_SP805_TWDG_BASE 0x2a490000
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#define ARM_SP805_TWDG_CLK_HZ 32768
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/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
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* asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
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#define ARM_TWDG_TIMEOUT_SEC 128
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#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
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ARM_TWDG_TIMEOUT_SEC)
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/******************************************************************************
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* Required platform porting definitions common to all ARM standard platforms
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*****************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
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/*******************************************************************************
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* BL1 specific defines.
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* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
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* addresses.
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******************************************************************************/
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#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
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#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
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+ PLAT_ARM_TRUSTED_ROM_SIZE)
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/*
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* Put BL1 RW at the top of the Trusted SRAM.
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*/
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#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
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ARM_BL_RAM_SIZE - \
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PLAT_ARM_MAX_BL1_RW_SIZE)
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#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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/*
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* Put BL2 just below BL31.
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*/
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#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_LIMIT BL31_BASE
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at the top of the Trusted SRAM.
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*/
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#define BL31_BASE (ARM_BL_RAM_BASE + \
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ARM_BL_RAM_SIZE - \
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PLAT_ARM_MAX_BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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/*
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* On ARM standard platforms, the TSP can execute from Trusted SRAM,
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* Trusted DRAM (if available) or the DRAM region secured by the TrustZone
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* controller.
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*/
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#if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
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# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
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# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
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# define TSP_PROGBITS_LIMIT BL2_BASE
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# define BL32_BASE ARM_BL_RAM_BASE
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# define BL32_LIMIT BL31_BASE
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#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
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# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
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# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
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# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
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# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
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+ (1 << 21))
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#elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
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# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
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# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
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# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
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# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE)
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#else
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# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
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#endif
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/*******************************************************************************
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* FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
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******************************************************************************/
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#define BL2U_BASE BL2_BASE
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#define BL2U_LIMIT BL31_BASE
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#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
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#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
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/*
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* ID of the secure physical generic timer interrupt used by the TSP.
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*/
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#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
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/*
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* One cache line needed for bakery locks on ARM platforms
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*/
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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#endif /* __ARM_DEF_H__ */
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