mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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1b491eead5
found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
414 lines
10 KiB
C
414 lines
10 KiB
C
/*
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <lib/smccc.h>
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#include <platform_def.h>
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#include <services/std_svc.h>
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#include <gpc.h>
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#include <imx_sip_svc.h>
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#define MIPI_PWR_REQ BIT(0)
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#define PCIE_PWR_REQ BIT(1)
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#define OTG1_PWR_REQ BIT(2)
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#define OTG2_PWR_REQ BIT(3)
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#define HSIOMIX_PWR_REQ BIT(4)
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#define GPU2D_PWR_REQ BIT(6)
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#define GPUMIX_PWR_REQ BIT(7)
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#define VPUMIX_PWR_REQ BIT(8)
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#define GPU3D_PWR_REQ BIT(9)
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#define DISPMIX_PWR_REQ BIT(10)
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#define VPU_G1_PWR_REQ BIT(11)
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#define VPU_G2_PWR_REQ BIT(12)
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#define VPU_H1_PWR_REQ BIT(13)
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#define HSIOMIX_ADB400_SYNC (0x3 << 5)
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#define DISPMIX_ADB400_SYNC BIT(7)
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#define VPUMIX_ADB400_SYNC BIT(8)
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#define GPU3D_ADB400_SYNC BIT(9)
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#define GPU2D_ADB400_SYNC BIT(10)
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#define GPUMIX_ADB400_SYNC BIT(11)
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#define HSIOMIX_ADB400_ACK (0x3 << 23)
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#define DISPMIX_ADB400_ACK BIT(25)
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#define VPUMIX_ADB400_ACK BIT(26)
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#define GPU3D_ADB400_ACK BIT(27)
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#define GPU2D_ADB400_ACK BIT(28)
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#define GPUMIX_ADB400_ACK BIT(29)
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#define MIPI_PGC 0xc00
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#define PCIE_PGC 0xc40
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#define OTG1_PGC 0xc80
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#define OTG2_PGC 0xcc0
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#define HSIOMIX_PGC 0xd00
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#define GPU2D_PGC 0xd80
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#define GPUMIX_PGC 0xdc0
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#define VPUMIX_PGC 0xe00
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#define GPU3D_PGC 0xe40
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#define DISPMIX_PGC 0xe80
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#define VPU_G1_PGC 0xec0
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#define VPU_G2_PGC 0xf00
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#define VPU_H1_PGC 0xf40
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enum pu_domain_id {
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HSIOMIX,
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PCIE,
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OTG1,
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OTG2,
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GPUMIX,
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VPUMIX,
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VPU_G1,
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VPU_G2,
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VPU_H1,
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DISPMIX,
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MIPI,
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/* below two domain only for ATF internal use */
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GPU2D,
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GPU3D,
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MAX_DOMAINS,
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};
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/* PU domain */
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static struct imx_pwr_domain pu_domains[] = {
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IMX_MIX_DOMAIN(HSIOMIX, false),
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IMX_PD_DOMAIN(PCIE, false),
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IMX_PD_DOMAIN(OTG1, true),
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IMX_PD_DOMAIN(OTG2, true),
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IMX_MIX_DOMAIN(GPUMIX, false),
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IMX_MIX_DOMAIN(VPUMIX, false),
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IMX_PD_DOMAIN(VPU_G1, false),
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IMX_PD_DOMAIN(VPU_G2, false),
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IMX_PD_DOMAIN(VPU_H1, false),
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IMX_MIX_DOMAIN(DISPMIX, false),
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IMX_PD_DOMAIN(MIPI, false),
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/* below two domain only for ATF internal use */
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IMX_MIX_DOMAIN(GPU2D, false),
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IMX_MIX_DOMAIN(GPU3D, false),
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};
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static unsigned int pu_domain_status;
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#define GPU_RCR 0x40
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#define VPU_RCR 0x44
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#define VPU_CTL_BASE 0x38330000
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#define BLK_SFT_RSTN_CSR 0x0
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#define H1_SFT_RSTN BIT(2)
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#define G1_SFT_RSTN BIT(1)
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#define G2_SFT_RSTN BIT(0)
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#define DISP_CTL_BASE 0x32e28000
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void vpu_sft_reset_assert(uint32_t domain_id)
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{
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uint32_t val;
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val = mmio_read_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR);
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switch (domain_id) {
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case VPU_G1:
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val &= ~G1_SFT_RSTN;
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mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
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break;
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case VPU_G2:
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val &= ~G2_SFT_RSTN;
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mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
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break;
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case VPU_H1:
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val &= ~H1_SFT_RSTN;
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mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
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break;
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default:
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break;
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}
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}
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void vpu_sft_reset_deassert(uint32_t domain_id)
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{
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uint32_t val;
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val = mmio_read_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR);
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switch (domain_id) {
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case VPU_G1:
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val |= G1_SFT_RSTN;
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mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
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break;
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case VPU_G2:
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val |= G2_SFT_RSTN;
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mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
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break;
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case VPU_H1:
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val |= H1_SFT_RSTN;
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mmio_write_32(VPU_CTL_BASE + BLK_SFT_RSTN_CSR, val);
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break;
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default:
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break;
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}
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}
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void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on)
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{
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if (domain_id >= MAX_DOMAINS) {
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return;
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}
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struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id];
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if (on) {
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pu_domain_status |= (1 << domain_id);
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if (domain_id == VPU_G1 || domain_id == VPU_G2 ||
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domain_id == VPU_H1) {
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vpu_sft_reset_assert(domain_id);
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}
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/* HSIOMIX has no PU bit, so skip for it */
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if (domain_id != HSIOMIX) {
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/* clear the PGC bit */
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mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
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/* power up the domain */
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req);
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/* wait for power request done */
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while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) {
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;
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}
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}
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if (domain_id == VPU_G1 || domain_id == VPU_G2 ||
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domain_id == VPU_H1) {
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vpu_sft_reset_deassert(domain_id);
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/* dealy for a while to make sure reset done */
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udelay(100);
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}
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if (domain_id == GPUMIX) {
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/* assert reset */
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mmio_write_32(IMX_SRC_BASE + GPU_RCR, 0x1);
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/* power up GPU2D */
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mmio_clrbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1);
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU2D_PWR_REQ);
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/* wait for power request done */
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while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU2D_PWR_REQ) {
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;
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}
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udelay(1);
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/* power up GPU3D */
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mmio_clrbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1);
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, GPU3D_PWR_REQ);
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/* wait for power request done */
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while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & GPU3D_PWR_REQ) {
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;
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}
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udelay(10);
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/* release the gpumix reset */
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mmio_write_32(IMX_SRC_BASE + GPU_RCR, 0x0);
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udelay(10);
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}
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/* vpu sft clock enable */
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if (domain_id == VPUMIX) {
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mmio_write_32(IMX_SRC_BASE + VPU_RCR, 0x1);
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udelay(5);
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mmio_write_32(IMX_SRC_BASE + VPU_RCR, 0x0);
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udelay(5);
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/* enable all clock */
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mmio_write_32(VPU_CTL_BASE + 0x4, 0x7);
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}
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if (domain_id == DISPMIX) {
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/* special setting for DISPMIX */
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mmio_write_32(DISP_CTL_BASE + 0x4, 0x1fff);
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mmio_write_32(DISP_CTL_BASE, 0x7f);
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mmio_write_32(DISP_CTL_BASE + 0x8, 0x30000);
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}
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/* handle the ADB400 sync */
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if (pwr_domain->need_sync) {
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/* clear adb power down request */
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mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
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/* wait for adb power request ack */
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while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) {
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;
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}
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}
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if (domain_id == GPUMIX) {
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/* power up GPU2D ADB */
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mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC);
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/* wait for adb power request ack */
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while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) {
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;
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}
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/* power up GPU3D ADB */
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mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC);
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/* wait for adb power request ack */
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while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) {
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;
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}
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}
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} else {
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pu_domain_status &= ~(1 << domain_id);
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if (domain_id == OTG1 || domain_id == OTG2) {
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return;
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}
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/* GPU2D & GPU3D ADB power down */
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if (domain_id == GPUMIX) {
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mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC);
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/* wait for adb power request ack */
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while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) {
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;
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}
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mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC);
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/* wait for adb power request ack */
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while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) {
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;
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}
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}
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/* handle the ADB400 sync */
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if (pwr_domain->need_sync) {
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/* set adb power down request */
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mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
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/* wait for adb power request ack */
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while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) {
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;
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}
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}
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if (domain_id == GPUMIX) {
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/* power down GPU2D */
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mmio_setbits_32(IMX_GPC_BASE + GPU2D_PGC, 0x1);
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU2D_PWR_REQ);
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/* wait for power request done */
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while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU2D_PWR_REQ) {
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;
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}
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/* power down GPU3D */
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mmio_setbits_32(IMX_GPC_BASE + GPU3D_PGC, 0x1);
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU3D_PWR_REQ);
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/* wait for power request done */
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while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU3D_PWR_REQ) {
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;
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}
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}
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/* HSIOMIX has no PU bit, so skip for it */
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if (domain_id != HSIOMIX) {
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/* set the PGC bit */
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mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
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/* power down the domain */
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mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
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/* wait for power request done */
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while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) {
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;
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}
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}
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}
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}
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void imx_gpc_init(void)
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{
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unsigned int val;
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int i;
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/* mask all the wakeup irq by default */
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for (i = 0; i < 4; i++) {
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
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mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
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}
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val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
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/* use GIC wake_request to wakeup C0~C3 from LPM */
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val |= 0x30c00000;
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/* clear the MASTER0 LPM handshake */
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val &= ~(1 << 6);
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mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
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/* clear MASTER1 & MASTER2 mapping in CPU0(A53) */
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mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |
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MASTER2_MAPPING));
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/* set all mix/PU in A53 domain */
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mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff);
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/*
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* Set the CORE & SCU power up timing:
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* SW = 0x1, SW2ISO = 0x1;
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* the CPU CORE and SCU power up timing counter
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* is drived by 32K OSC, each domain's power up
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* latency is (SW + SW2ISO) / 32768
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*/
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81);
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mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
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(0x59 << 10) | 0x5B | (0x2 << 20));
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/* set DUMMY PDN/PUP ACK by default for A53 domain */
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mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,
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A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK);
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/* clear DSM by default */
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val = mmio_read_32(IMX_GPC_BASE + SLPCR);
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val &= ~SLPCR_EN_DSM;
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/* enable the fast wakeup wait mode */
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val |= SLPCR_A53_FASTWUP_WAIT_MODE;
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/* clear the RBC */
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val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT);
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/* set the STBY_COUNT to 0x5, (128 * 30)us */
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val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
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val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
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mmio_write_32(IMX_GPC_BASE + SLPCR, val);
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/*
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* USB PHY power up needs to make sure RESET bit in SRC is clear,
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* otherwise, the PU power up bit in GPC will NOT self-cleared.
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* only need to do it once.
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*/
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mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
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mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
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}
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