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https://github.com/ARM-software/arm-trusted-firmware.git
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1b491eead5
found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
/*
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* Copyright 2020-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef DCFG_LSCH2_H
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#define DCFG_LSCH2_H
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/* dcfg block register offsets and bitfields */
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#define DCFG_PORSR1_OFFSET 0x00
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#define DCFG_DEVDISR1_OFFSET 0x070
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#define DCFG_DEVDISR2_OFFSET 0x074
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#define DCFG_DEVDISR3_OFFSET 0x078
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#define DCFG_DEVDISR4_OFFSET 0x07C
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#define DCFG_DEVDISR5_OFFSET 0x080
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#define DCFG_COREDISR_OFFSET 0x094
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#define RCWSR0_OFFSET 0x100
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#define RCWSR5_OFFSET 0x118
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#define DCFG_BOOTLOCPTRL_OFFSET 0x400
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#define DCFG_BOOTLOCPTRH_OFFSET 0x404
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#define DCFG_COREDISABLEDSR_OFFSET 0x990
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#define DCFG_SCRATCH4_OFFSET 0x20C
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#define DCFG_SVR_OFFSET 0x0A4
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#define DCFG_BRR_OFFSET 0x0E4
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#define DCFG_RSTCR_OFFSET 0x0B0
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#define RSTCR_RESET_REQ 0x2
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#define DCFG_RSTRQSR1_OFFSET 0x0C8
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#define DCFG_RSTRQMR1_OFFSET 0x0C0
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/* PORSR1 bit mask */
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#define PORSR1_RCW_MASK 0xff800000
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#define PORSR1_RCW_SHIFT 23
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/* DCFG DCSR Macros */
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#define DCFG_DCSR_PORCR1_OFFSET 0x0
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#define SVR_MFR_ID_MASK 0xF0000000
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#define SVR_MFR_ID_SHIFT 28
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#define SVR_DEV_ID_MASK 0xFFF0000
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#define SVR_DEV_ID_SHIFT 16
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#define SVR_PERSONALITY_MASK 0xFF00
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#define SVR_PERSONALITY_SHIFT 8
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#define SVR_SEC_MASK 0x100
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#define SVR_SEC_SHIFT 8
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#define SVR_MAJ_VER_MASK 0xF0
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#define SVR_MAJ_VER_SHIFT 4
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#define SVR_MIN_VER_MASK 0xF
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#define SVR_MINOR_VER_0 0x00
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#define SVR_MINOR_VER_1 0x01
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#define DISR5_DDRC1_MASK 0x1
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#define DISR5_OCRAM_MASK 0x40
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/* DCFG registers bit masks */
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#define RCWSR0_SYS_PLL_RAT_SHIFT 25
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#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
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#define RCWSR0_MEM_PLL_RAT_SHIFT 16
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#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
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#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
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#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
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#define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET
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#define RCWSR_SBEN_MASK 0x1
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#define RCWSR_SBEN_SHIFT 21
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/* RCW SRC NAND */
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#define RCW_SRC_NAND_MASK (0x100)
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#define RCW_SRC_NAND_VAL (0x100)
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#define NAND_RESERVED_MASK (0xFC)
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#define NAND_RESERVED_1 (0x0)
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#define NAND_RESERVED_2 (0x80)
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/* RCW SRC NOR */
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#define RCW_SRC_NOR_MASK (0x1F0)
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#define NOR_8B_VAL (0x10)
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#define NOR_16B_VAL (0x20)
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#define SD_VAL (0x40)
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#define QSPI_VAL1 (0x44)
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#define QSPI_VAL2 (0x45)
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#endif /* DCFG_LSCH2_H */
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