mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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1b491eead5
found using codespell (https://github.com/codespell-project/codespell). Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
594 lines
16 KiB
C
594 lines
16 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <errno.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <common/debug.h>
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#include <ddr.h>
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#include <drivers/delay_timer.h>
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#include <immap.h>
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#define BIST_CR 0x80060000
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#define BIST_CR_EN 0x80000000
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#define BIST_CR_STAT 0x00000001
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#define CTLR_INTLV_MASK 0x20000000
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#pragma weak run_bist
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bool run_bist(void)
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{
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#ifdef BIST_EN
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return true;
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#else
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return false;
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#endif
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}
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/*
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* Perform build-in test on memory
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* timeout value in 10ms
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*/
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int bist(const struct ccsr_ddr *ddr, int timeout)
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{
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const unsigned int test_pattern[10] = {
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0xffffffff,
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0x00000000,
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0xaaaaaaaa,
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0x55555555,
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0xcccccccc,
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0x33333333,
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0x12345678,
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0xabcdef01,
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0xaa55aa55,
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0x55aa55aa
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};
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unsigned int mtcr, err_detect, err_sbe;
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unsigned int cs0_config;
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unsigned int csn_bnds[4];
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int ret = 0;
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uint32_t i;
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#ifdef CONFIG_DDR_ADDR_DEC
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uint32_t dec_9 = ddr_in32(&ddr->dec[9]);
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uint32_t pos = 0U;
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uint32_t map_save = 0U;
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uint32_t temp32 = 0U;
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uint32_t map, shift, highest;
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#endif
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cs0_config = ddr_in32(&ddr->csn_cfg[0]);
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if ((cs0_config & CTLR_INTLV_MASK) != 0U) {
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/* set bnds to non-interleaving */
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for (i = 0U; i < 4U; i++) {
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csn_bnds[i] = ddr_in32(&ddr->bnds[i].a);
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ddr_out32(&ddr->bnds[i].a,
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(csn_bnds[i] & U(0xfffefffe)) >> 1U);
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}
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ddr_out32(&ddr->csn_cfg[0], cs0_config & ~CTLR_INTLV_MASK);
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#ifdef CONFIG_DDR_ADDR_DEC
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if ((dec_9 & 0x1U) != 0U) {
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highest = (dec_9 >> 26U) == U(0x3F) ? 0U : dec_9 >> 26U;
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pos = 37U;
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for (i = 0U; i < 36U; i++) { /* Go through all 37 */
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if ((i % 4U) == 0U) {
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temp32 = ddr_in32(&ddr->dec[i >> 2U]);
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}
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shift = (3U - i % 4U) * 8U + 2U;
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map = (temp32 >> shift) & U(0x3F);
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if (map > highest && map != U(0x3F)) {
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highest = map;
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pos = i;
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}
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}
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debug("\nFound highest position %d, mapping to %d, ",
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pos, highest);
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map_save = ddr_in32(&ddr->dec[pos >> 2]);
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shift = (3U - pos % 4U) * 8U + 2U;
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debug("in dec[%d], bit %d (0x%x)\n",
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pos >> 2U, shift, map_save);
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temp32 = map_save & ~(U(0x3F) << shift);
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temp32 |= 8U << shift;
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ddr_out32(&ddr->dec[pos >> 2U], temp32);
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timeout <<= 2U;
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debug("Increase wait time to %d ms\n", timeout * 10);
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}
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#endif
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}
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for (i = 0U; i < 10U; i++) {
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ddr_out32(&ddr->mtp[i], test_pattern[i]);
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}
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mtcr = BIST_CR;
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ddr_out32(&ddr->mtcr, mtcr);
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do {
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mdelay(10);
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mtcr = ddr_in32(&ddr->mtcr);
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} while (timeout-- > 0 && ((mtcr & BIST_CR_EN) != 0));
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if (timeout <= 0) {
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ERROR("Timeout\n");
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} else {
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debug("Timer remains %d\n", timeout);
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}
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err_detect = ddr_in32(&ddr->err_detect);
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err_sbe = ddr_in32(&ddr->err_sbe);
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if (err_detect != 0U || ((err_sbe & U(0xffff)) != 0U)) {
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ERROR("ECC error detected\n");
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ret = -EIO;
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}
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if ((cs0_config & CTLR_INTLV_MASK) != 0) {
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for (i = 0U; i < 4U; i++) {
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ddr_out32(&ddr->bnds[i].a, csn_bnds[i]);
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}
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ddr_out32(&ddr->csn_cfg[0], cs0_config);
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#ifdef CONFIG_DDR_ADDR_DEC
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if ((dec_9 & U(0x1)) != 0U) {
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ddr_out32(&ddr->dec[pos >> 2], map_save);
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}
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#endif
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}
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if ((mtcr & BIST_CR_STAT) != 0) {
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ERROR("Built-in self test failed\n");
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ret = -EIO;
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} else {
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NOTICE("Build-in self test passed\n");
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}
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return ret;
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}
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void dump_ddrc(unsigned int *ddr)
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{
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#ifdef DDR_DEBUG
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uint32_t i;
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unsigned long val;
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for (i = 0U; i < U(0x400); i++, ddr++) {
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val = ddr_in32(ddr);
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if (val != 0U) { /* skip zeros */
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debug("*0x%lx = 0x%lx\n", (unsigned long)ddr, val);
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}
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}
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#endif
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}
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#ifdef ERRATA_DDR_A009803
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static void set_wait_for_bits_clear(const void *ptr,
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unsigned int value,
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unsigned int bits)
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{
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int timeout = 1000;
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ddr_out32(ptr, value);
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do {
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udelay(100);
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} while (timeout-- > 0 && ((ddr_in32(ptr) & bits) != 0));
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if (timeout <= 0) {
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ERROR("wait for clear timeout.\n");
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}
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}
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#endif
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#if (DDRC_NUM_CS > 4)
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#error Invalid setting for DDRC_NUM_CS
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#endif
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/*
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* If supported by the platform, writing to DDR controller takes two
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* passes to deassert DDR reset to comply with JEDEC specs for RDIMMs.
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*/
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int ddrc_set_regs(const unsigned long clk,
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const struct ddr_cfg_regs *regs,
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const struct ccsr_ddr *ddr,
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int twopass)
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{
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unsigned int i, bus_width;
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unsigned int temp_sdram_cfg;
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unsigned int total_mem_per_ctrl, total_mem_per_ctrl_adj;
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const int mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
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int timeout;
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int ret = 0;
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#if defined(ERRATA_DDR_A009942) || defined(ERRATA_DDR_A010165)
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unsigned long ddr_freq;
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unsigned int tmp;
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#ifdef ERRATA_DDR_A009942
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unsigned int check;
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unsigned int cpo_min = U(0xff);
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unsigned int cpo_max = 0U;
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#endif
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#endif
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if (twopass == 2U) {
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goto after_reset;
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}
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/* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
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ddr_out32(&ddr->ddr_cdr1, regs->cdr[0]);
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ddr_out32(&ddr->sdram_clk_cntl, regs->clk_cntl);
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for (i = 0U; i < DDRC_NUM_CS; i++) {
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if (mod_bnds != 0U) {
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ddr_out32(&ddr->bnds[i].a,
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(regs->cs[i].bnds & U(0xfffefffe)) >> 1U);
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} else {
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ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
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}
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ddr_out32(&ddr->csn_cfg_2[i], regs->cs[i].config_2);
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}
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ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]);
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ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]);
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ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]);
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ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]);
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ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]);
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ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]);
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ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]);
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ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]);
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ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]);
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ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]);
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ddr_out32(&ddr->zq_cntl, regs->zq_cntl);
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for (i = 0U; i < 4U; i++) {
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ddr_out32(&ddr->dq_map[i], regs->dq_map[i]);
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}
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ddr_out32(&ddr->sdram_cfg_3, regs->sdram_cfg[2]);
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ddr_out32(&ddr->sdram_mode, regs->sdram_mode[0]);
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ddr_out32(&ddr->sdram_mode_2, regs->sdram_mode[1]);
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ddr_out32(&ddr->sdram_mode_3, regs->sdram_mode[2]);
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ddr_out32(&ddr->sdram_mode_4, regs->sdram_mode[3]);
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ddr_out32(&ddr->sdram_mode_5, regs->sdram_mode[4]);
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ddr_out32(&ddr->sdram_mode_6, regs->sdram_mode[5]);
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ddr_out32(&ddr->sdram_mode_7, regs->sdram_mode[6]);
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ddr_out32(&ddr->sdram_mode_8, regs->sdram_mode[7]);
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ddr_out32(&ddr->sdram_mode_9, regs->sdram_mode[8]);
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ddr_out32(&ddr->sdram_mode_10, regs->sdram_mode[9]);
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ddr_out32(&ddr->sdram_mode_11, regs->sdram_mode[10]);
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ddr_out32(&ddr->sdram_mode_12, regs->sdram_mode[11]);
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ddr_out32(&ddr->sdram_mode_13, regs->sdram_mode[12]);
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ddr_out32(&ddr->sdram_mode_14, regs->sdram_mode[13]);
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ddr_out32(&ddr->sdram_mode_15, regs->sdram_mode[14]);
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ddr_out32(&ddr->sdram_mode_16, regs->sdram_mode[15]);
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ddr_out32(&ddr->sdram_md_cntl, regs->md_cntl);
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#ifdef ERRATA_DDR_A009663
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ddr_out32(&ddr->sdram_interval,
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regs->interval & ~SDRAM_INTERVAL_BSTOPRE);
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#else
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ddr_out32(&ddr->sdram_interval, regs->interval);
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#endif
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ddr_out32(&ddr->sdram_data_init, regs->data_init);
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if (regs->eor != 0) {
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ddr_out32(&ddr->eor, regs->eor);
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}
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ddr_out32(&ddr->wrlvl_cntl, regs->wrlvl_cntl[0]);
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#ifndef NXP_DDR_EMU
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/*
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* Skip these two registers if running on emulator
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* because emulator doesn't have skew between bytes.
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*/
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if (regs->wrlvl_cntl[1] != 0) {
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ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->wrlvl_cntl[1]);
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}
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if (regs->wrlvl_cntl[2] != 0) {
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ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->wrlvl_cntl[2]);
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}
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#endif
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ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
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ddr_out32(&ddr->ddr_sdram_rcw_1, regs->sdram_rcw[0]);
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ddr_out32(&ddr->ddr_sdram_rcw_2, regs->sdram_rcw[1]);
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ddr_out32(&ddr->ddr_sdram_rcw_3, regs->sdram_rcw[2]);
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ddr_out32(&ddr->ddr_sdram_rcw_4, regs->sdram_rcw[3]);
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ddr_out32(&ddr->ddr_sdram_rcw_5, regs->sdram_rcw[4]);
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ddr_out32(&ddr->ddr_sdram_rcw_6, regs->sdram_rcw[5]);
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ddr_out32(&ddr->ddr_cdr2, regs->cdr[1]);
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ddr_out32(&ddr->sdram_cfg_2, regs->sdram_cfg[1]);
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ddr_out32(&ddr->init_addr, regs->init_addr);
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ddr_out32(&ddr->init_ext_addr, regs->init_ext_addr);
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#ifdef ERRATA_DDR_A009803
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/* part 1 of 2 */
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if ((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) {
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if ((regs->sdram_cfg[0] & SDRAM_CFG_RD_EN) != 0) {
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ddr_out32(&ddr->ddr_sdram_rcw_2,
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regs->sdram_rcw[1] & ~0xf0);
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}
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ddr_out32(&ddr->err_disable,
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regs->err_disable | DDR_ERR_DISABLE_APED);
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}
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#else
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ddr_out32(&ddr->err_disable, regs->err_disable);
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#endif
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ddr_out32(&ddr->err_int_en, regs->err_int_en);
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/* For DDRC 5.05 only */
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if (get_ddrc_version(ddr) == 0x50500) {
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ddr_out32(&ddr->tx_cfg[1], 0x1f1f1f1f);
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ddr_out32(&ddr->debug[3], 0x124a02c0);
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}
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for (i = 0U; i < 4U; i++) {
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if (regs->tx_cfg[i] != 0) {
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ddr_out32(&ddr->tx_cfg[i], regs->tx_cfg[i]);
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}
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}
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for (i = 0U; i < 64U; i++) {
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if (regs->debug[i] != 0) {
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#ifdef ERRATA_DDR_A009942
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if (i == 28U) {
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continue;
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}
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#endif
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ddr_out32(&ddr->debug[i], regs->debug[i]);
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}
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}
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#ifdef CONFIG_DDR_ADDR_DEC
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if ((regs->dec[9] & 1) != 0U) {
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for (i = 0U; i < 10U; i++) {
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ddr_out32(&ddr->dec[i], regs->dec[i]);
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}
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if (mod_bnds != 0) {
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debug("Disable address decoding\n");
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ddr_out32(&ddr->dec[9], 0);
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}
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}
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#endif
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#ifdef ERRATA_DDR_A008511
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/* Part 1 of 2 */
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/* This erraum only applies to version 5.2.1 */
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if (get_ddrc_version(ddr) == 0x50200) {
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ERROR("Unsupported SoC.\n");
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} else if (get_ddrc_version(ddr) == 0x50201) {
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ddr_out32(&ddr->debug[37], (U(1) << 31));
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ddr_out32(&ddr->ddr_cdr2,
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regs->cdr[1] | DDR_CDR2_VREF_TRAIN_EN);
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} else {
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debug("Erratum A008511 doesn't apply.\n");
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}
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#endif
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#ifdef ERRATA_DDR_A009942
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ddr_freq = clk / 1000000U;
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tmp = ddr_in32(&ddr->debug[28]);
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tmp &= U(0xff0fff00);
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tmp |= ddr_freq <= 1333U ? U(0x0080006a) :
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(ddr_freq <= 1600U ? U(0x0070006f) :
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(ddr_freq <= 1867U ? U(0x00700076) : U(0x0060007b)));
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if (regs->debug[28] != 0) {
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tmp &= ~0xff;
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tmp |= regs->debug[28] & 0xff;
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} else {
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WARN("Warning: Optimal CPO value not set.\n");
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}
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ddr_out32(&ddr->debug[28], tmp);
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#endif
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#ifdef ERRATA_DDR_A010165
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ddr_freq = clk / 1000000U;
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if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
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tmp = ddr_in32(&ddr->debug[28]);
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ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
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}
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#endif
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/*
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* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
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* deasserted. Clocks start when any chip select is enabled and clock
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* control register is set. Because all DDR components are connected to
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* one reset signal, this needs to be done in two steps. Step 1 is to
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* get the clocks started. Step 2 resumes after reset signal is
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* deasserted.
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*/
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if (twopass == 1) {
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udelay(200);
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return 0;
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}
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/* As per new sequence flow shall be write CSn_CONFIG registers needs to
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* be set after all the other DDR controller registers are set, then poll
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* for PHY_INIT_CMPLT = 1 , then wait at least 100us (micro seconds),
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* then set the MEM_EN = 1
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*/
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for (i = 0U; i < DDRC_NUM_CS; i++) {
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if (mod_bnds != 0U && i == 0U) {
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ddr_out32(&ddr->csn_cfg[i],
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(regs->cs[i].config & ~CTLR_INTLV_MASK));
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} else {
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ddr_out32(&ddr->csn_cfg[i], regs->cs[i].config);
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}
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}
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after_reset:
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/* Set, but do not enable the memory */
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temp_sdram_cfg = regs->sdram_cfg[0];
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temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
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ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
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if (get_ddrc_version(ddr) < U(0x50500)) {
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/*
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* 500 painful micro-seconds must elapse between
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* the DDR clock setup and the DDR config enable.
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* DDR2 need 200 us, and DDR3 need 500 us from spec,
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* we choose the max, that is 500 us for all of case.
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*/
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udelay(500);
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/* applied memory barrier */
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mb();
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isb();
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} else {
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/* wait for PHY complete */
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timeout = 40;
|
|
while (((ddr_in32(&ddr->ddr_dsr2) & 0x4) != 0) &&
|
|
(timeout > 0)) {
|
|
udelay(500);
|
|
timeout--;
|
|
}
|
|
if (timeout <= 0) {
|
|
printf("PHY handshake timeout, ddr_dsr2 = %x\n",
|
|
ddr_in32(&ddr->ddr_dsr2));
|
|
} else {
|
|
debug("PHY handshake completed, timer remains %d\n",
|
|
timeout);
|
|
}
|
|
}
|
|
|
|
temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg);
|
|
/* Let the controller go */
|
|
udelay(100);
|
|
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
|
|
|
|
/* applied memory barrier */
|
|
mb();
|
|
isb();
|
|
|
|
total_mem_per_ctrl = 0;
|
|
for (i = 0; i < DDRC_NUM_CS; i++) {
|
|
if ((regs->cs[i].config & 0x80000000) == 0) {
|
|
continue;
|
|
}
|
|
total_mem_per_ctrl += 1 << (
|
|
((regs->cs[i].config >> 14) & 0x3) + 2 +
|
|
((regs->cs[i].config >> 8) & 0x7) + 12 +
|
|
((regs->cs[i].config >> 4) & 0x3) + 0 +
|
|
((regs->cs[i].config >> 0) & 0x7) + 8 +
|
|
((regs->sdram_cfg[2] >> 4) & 0x3) +
|
|
3 - ((regs->sdram_cfg[0] >> 19) & 0x3) -
|
|
26); /* minus 26 (count of 64M) */
|
|
}
|
|
total_mem_per_ctrl_adj = total_mem_per_ctrl;
|
|
/*
|
|
* total memory / bus width = transactions needed
|
|
* transactions needed / data rate = seconds
|
|
* to add plenty of buffer, double the time
|
|
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
|
|
* Let's wait for 800ms
|
|
*/
|
|
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
|
|
>> SDRAM_CFG_DBW_SHIFT);
|
|
timeout = ((total_mem_per_ctrl_adj << (6 - bus_width)) * 100 /
|
|
(clk >> 20)) << 2;
|
|
total_mem_per_ctrl_adj >>= 4; /* shift down to gb size */
|
|
if ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) != 0) {
|
|
debug("total size %d GB\n", total_mem_per_ctrl_adj);
|
|
debug("Need to wait up to %d ms\n", timeout * 10);
|
|
|
|
do {
|
|
mdelay(10);
|
|
} while (timeout-- > 0 &&
|
|
((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)) != 0);
|
|
|
|
if (timeout <= 0) {
|
|
if (ddr_in32(&ddr->debug[1]) & 0x3d00) {
|
|
ERROR("Found training error(s): 0x%x\n",
|
|
ddr_in32(&ddr->debug[1]));
|
|
}
|
|
ERROR("Error: Waiting for D_INIT timeout.\n");
|
|
return -EIO;
|
|
}
|
|
}
|
|
|
|
if (mod_bnds != 0U) {
|
|
debug("Restore original bnds\n");
|
|
for (i = 0U; i < DDRC_NUM_CS; i++) {
|
|
ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
|
|
}
|
|
ddr_out32(&ddr->csn_cfg[0], regs->cs[0].config);
|
|
#ifdef CONFIG_DDR_ADDR_DEC
|
|
if ((regs->dec[9] & U(0x1)) != 0U) {
|
|
debug("Restore address decoding\n");
|
|
ddr_out32(&ddr->dec[9], regs->dec[9]);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#ifdef ERRATA_DDR_A009803
|
|
/* Part 2 of 2 */
|
|
if ((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) {
|
|
timeout = 400;
|
|
do {
|
|
mdelay(1);
|
|
} while (timeout-- > 0 && ((ddr_in32(&ddr->debug[1]) & 0x2) == 0));
|
|
|
|
if ((regs->sdram_cfg[0] & SDRAM_CFG_RD_EN) != 0) {
|
|
for (i = 0U; i < DDRC_NUM_CS; i++) {
|
|
if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0) {
|
|
continue;
|
|
}
|
|
set_wait_for_bits_clear(&ddr->sdram_md_cntl,
|
|
MD_CNTL_MD_EN |
|
|
MD_CNTL_CS_SEL(i) |
|
|
0x070000ed,
|
|
MD_CNTL_MD_EN);
|
|
udelay(1);
|
|
}
|
|
}
|
|
|
|
ddr_out32(&ddr->err_disable,
|
|
regs->err_disable & ~DDR_ERR_DISABLE_APED);
|
|
}
|
|
#endif
|
|
|
|
#ifdef ERRATA_DDR_A009663
|
|
ddr_out32(&ddr->sdram_interval, regs->interval);
|
|
#endif
|
|
|
|
#ifdef ERRATA_DDR_A009942
|
|
timeout = 400;
|
|
do {
|
|
mdelay(1);
|
|
} while (timeout-- > 0 && ((ddr_in32(&ddr->debug[1]) & 0x2) == 0));
|
|
tmp = (regs->sdram_cfg[0] >> 19) & 0x3;
|
|
check = (tmp == DDR_DBUS_64) ? 4 : ((tmp == DDR_DBUS_32) ? 2 : 1);
|
|
for (i = 0; i < check; i++) {
|
|
tmp = ddr_in32(&ddr->debug[9 + i]);
|
|
debug("Reading debug[%d] as 0x%x\n", i + 9, tmp);
|
|
cpo_min = min(cpo_min,
|
|
min((tmp >> 24) & 0xff, (tmp >> 8) & 0xff));
|
|
cpo_max = max(cpo_max,
|
|
max((tmp >> 24) & 0xff, (tmp >> 8) & 0xff));
|
|
}
|
|
if ((regs->sdram_cfg[0] & SDRAM_CFG_ECC_EN) != 0) {
|
|
tmp = ddr_in32(&ddr->debug[13]);
|
|
cpo_min = min(cpo_min, (tmp >> 24) & 0xff);
|
|
cpo_max = max(cpo_max, (tmp >> 24) & 0xff);
|
|
}
|
|
debug("cpo_min 0x%x\n", cpo_min);
|
|
debug("cpo_max 0x%x\n", cpo_max);
|
|
tmp = ddr_in32(&ddr->debug[28]);
|
|
debug("debug[28] 0x%x\n", tmp);
|
|
if ((cpo_min + 0x3B) < (tmp & 0xff)) {
|
|
WARN("Warning: A009942 requires setting cpo_sample to 0x%x\n",
|
|
(cpo_min + cpo_max) / 2 + 0x27);
|
|
} else {
|
|
debug("Optimal cpo_sample 0x%x\n",
|
|
(cpo_min + cpo_max) / 2 + 0x27);
|
|
}
|
|
#endif
|
|
if (run_bist() != 0) {
|
|
if ((ddr_in32(&ddr->debug[1]) &
|
|
((get_ddrc_version(ddr) == 0x50500) ? 0x3c00 : 0x3d00)) != 0) {
|
|
ERROR("Found training error(s): 0x%x\n",
|
|
ddr_in32(&ddr->debug[1]));
|
|
return -EIO;
|
|
}
|
|
INFO("Running built-in self test ...\n");
|
|
/* give it 10x time to cover whole memory */
|
|
timeout = ((total_mem_per_ctrl << (6 - bus_width)) *
|
|
100 / (clk >> 20)) * 10;
|
|
INFO("\tWait up to %d ms\n", timeout * 10);
|
|
ret = bist(ddr, timeout);
|
|
}
|
|
dump_ddrc((void *)ddr);
|
|
|
|
return ret;
|
|
}
|