mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-15 17:14:21 +00:00
1af540ef2a
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined
Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all
Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
96 lines
2.6 KiB
C
96 lines
2.6 KiB
C
/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arm_def.h>
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#include <arm_spm_def.h>
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#include <debug.h>
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#include <plat_arm.h>
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#include <platform_def.h>
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#include <tzc400.h>
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak plat_arm_security_setup
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/*******************************************************************************
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* Initialize the TrustZone Controller for ARM standard platforms.
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* Configure:
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* - Region 0 with no access;
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* - Region 1 with secure access only;
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* - the remaining DRAM regions access from the given Non-Secure masters.
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*
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* When booting an EL3 payload, this is simplified: we configure region 0 with
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* secure access only and do not enable any other region.
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******************************************************************************/
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void arm_tzc400_setup(void)
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{
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INFO("Configuring TrustZone Controller\n");
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tzc400_init(PLAT_ARM_TZC_BASE);
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/* Disable filters. */
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tzc400_disable_filters();
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#ifndef EL3_PAYLOAD_BASE
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/* Region 0 set to no access by default */
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tzc400_configure_region0(TZC_REGION_S_NONE, 0);
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/* Region 1 set to cover Secure part of DRAM */
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tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 1,
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ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END,
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TZC_REGION_S_RDWR,
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0);
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/* Region 2 set to cover Non-Secure access to 1st DRAM address range.
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* Apply the same configuration to given filters in the TZC. */
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tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 2,
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ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
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ARM_TZC_NS_DRAM_S_ACCESS,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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/* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
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tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 3,
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ARM_DRAM2_BASE, ARM_DRAM2_END,
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ARM_TZC_NS_DRAM_S_ACCESS,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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#if ENABLE_SPM
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/*
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* Region 4 set to cover Non-Secure access to the communication buffer
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* shared with the Secure world.
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*/
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tzc400_configure_region(PLAT_ARM_TZC_FILTERS,
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4,
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ARM_SP_IMAGE_NS_BUF_BASE,
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(ARM_SP_IMAGE_NS_BUF_BASE +
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ARM_SP_IMAGE_NS_BUF_SIZE) - 1,
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TZC_REGION_S_NONE,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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#endif
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#else /* if defined(EL3_PAYLOAD_BASE) */
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/* Allow Secure and Non-secure access to DRAM for EL3 payloads */
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tzc400_configure_region0(TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS);
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#endif /* EL3_PAYLOAD_BASE */
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/*
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* Raise an exception if a NS device tries to access secure memory
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* TODO: Add interrupt handling support.
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*/
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tzc400_set_action(TZC_ACTION_ERR);
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/* Enable filters. */
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tzc400_enable_filters();
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}
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void plat_arm_security_setup(void)
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{
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arm_tzc400_setup();
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}
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