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https://github.com/ARM-software/arm-trusted-firmware.git
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1af540ef2a
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined
Fixed for:
make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all
Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
94 lines
3.1 KiB
C
94 lines
3.1 KiB
C
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arm_config.h>
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#include <cassert.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <platform_def.h>
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#include "drivers/pwrc/fvp_pwrc.h"
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/* The FVP power domain tree descriptor */
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static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2];
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CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count);
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/*******************************************************************************
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* This function dynamically constructs the topology according to
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* FVP_CLUSTER_COUNT and returns it.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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unsigned int i;
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/*
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* The highest level is the system level. The next level is constituted
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* by clusters and then cores in clusters.
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*/
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fvp_power_domain_tree_desc[0] = 1;
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fvp_power_domain_tree_desc[1] = FVP_CLUSTER_COUNT;
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for (i = 0; i < FVP_CLUSTER_COUNT; i++)
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fvp_power_domain_tree_desc[i + 2] = FVP_MAX_CPUS_PER_CLUSTER;
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return fvp_power_domain_tree_desc;
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}
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/*******************************************************************************
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* This function returns the core count within the cluster corresponding to
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* `mpidr`.
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******************************************************************************/
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unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
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{
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return FVP_MAX_CPUS_PER_CLUSTER;
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}
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int clus_id, cpu_id, thread_id;
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/* Validate affinity fields */
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if (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) {
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thread_id = MPIDR_AFFLVL0_VAL(mpidr);
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cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
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clus_id = MPIDR_AFFLVL2_VAL(mpidr);
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} else {
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thread_id = 0;
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cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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clus_id = MPIDR_AFFLVL1_VAL(mpidr);
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}
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if (clus_id >= FVP_CLUSTER_COUNT)
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return -1;
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if (cpu_id >= FVP_MAX_CPUS_PER_CLUSTER)
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return -1;
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if (thread_id >= FVP_MAX_PE_PER_CPU)
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return -1;
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if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID)
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return -1;
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/*
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* Core position calculation for FVP platform depends on the MT bit in
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* MPIDR. This function cannot assume that the supplied MPIDR has the MT
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* bit set even if the implementation has. For example, PSCI clients
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* might supply MPIDR values without the MT bit set. Therefore, we
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* inject the current PE's MT bit so as to get the calculation correct.
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* This of course assumes that none or all CPUs on the platform has MT
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* bit set.
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*/
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mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
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return plat_arm_calc_core_pos(mpidr);
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}
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