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1a74e4a895
There are some incorrect casts and some missing casts in the headers. This patch fixes the ones that were 64-bit or 32-bit wide wrongly and adds casts where they were missing. Note that none of the changes of the patch actually changes the values of the definitions. This patch is just for correctness. Change-Id: Iad6458021bad521922ce4f91bafff38b116b49eb Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
33 lines
1.1 KiB
C
33 lines
1.1 KiB
C
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DSU_DEF_H
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#define DSU_DEF_H
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#include <lib/utils_def.h>
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/********************************************************************
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* DSU control registers definitions *
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********************************************************************/
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#define CLUSTERCFR_EL1 S3_0_C15_C3_0
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#define CLUSTERIDR_EL1 S3_0_C15_C3_1
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#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
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/********************************************************************
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* DSU control registers bit fields *
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********************************************************************/
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#define CLUSTERIDR_REV_SHIFT U(0)
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#define CLUSTERIDR_REV_BITS U(4)
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#define CLUSTERIDR_VAR_SHIFT U(4)
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#define CLUSTERIDR_VAR_BITS U(4)
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#define CLUSTERCFR_ACP_SHIFT U(11)
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/********************************************************************
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* Masks applied for DSU errata workarounds *
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********************************************************************/
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#define DSU_ERRATA_936184_MASK (U(0x3) << 15)
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#endif /* DSU_DEF_H */
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