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1a74e4a895
There are some incorrect casts and some missing casts in the headers. This patch fixes the ones that were 64-bit or 32-bit wide wrongly and adds casts where they were missing. Note that none of the changes of the patch actually changes the values of the definitions. This patch is just for correctness. Change-Id: Iad6458021bad521922ce4f91bafff38b116b49eb Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
34 lines
1.3 KiB
C
34 lines
1.3 KiB
C
/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A73_H
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#define CORTEX_A73_H
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#include <lib/utils_def.h>
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/* Cortex-A73 midr for revision 0 */
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#define CORTEX_A73_MIDR U(0x410FD090)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
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#define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
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/*******************************************************************************
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* CPU implementation defined register specific definitions.
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******************************************************************************/
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#define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0
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#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3)
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#endif /* CORTEX_A73_H */
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