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1a74e4a895
There are some incorrect casts and some missing casts in the headers. This patch fixes the ones that were 64-bit or 32-bit wide wrongly and adds casts where they were missing. Note that none of the changes of the patch actually changes the values of the definitions. This patch is just for correctness. Change-Id: Iad6458021bad521922ce4f91bafff38b116b49eb Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
83 lines
3.5 KiB
C
83 lines
3.5 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A57_H
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#define CORTEX_A57_H
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#include <lib/utils_def.h>
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/* Cortex-A57 midr for revision 0 */
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#define CORTEX_A57_MIDR U(0x410FD070)
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 U(0x1)
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#define RETENTION_ENTRY_TICKS_8 U(0x2)
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#define RETENTION_ENTRY_TICKS_32 U(0x3)
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#define RETENTION_ENTRY_TICKS_64 U(0x4)
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#define RETENTION_ENTRY_TICKS_128 U(0x5)
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#define RETENTION_ENTRY_TICKS_256 U(0x6)
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#define RETENTION_ENTRY_TICKS_512 U(0x7)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_ECTLR p15, 1, c15
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#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
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#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
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#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_CPUMERRSR p15, 2, c15
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_CPUACTLR p15, 0, c15
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
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#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
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#define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
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#define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)
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#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25)
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#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
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#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
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#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
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#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
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#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2MERRSR p15, 3, c15
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#endif /* CORTEX_A57_H */
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