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19d52a83b7
Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte* store instruction. A related instruction is ST64BV0, which will replace the lowest 32 bits of the data with a value taken from the ACCDATA_EL1 system register (so that EL0 cannot alter them). Using that ST64BV0 instruction and accessing the ACCDATA_EL1 system register is guarded by two SCR_EL3 bits, which we should set to avoid a trap into EL3, when lower ELs use one of those. Add the required bits and pieces to make this feature usable: - Add the ENABLE_FEAT_LS64_ACCDATA build option (defaulting to 0). - Add the CPUID and SCR_EL3 bit definitions associated with FEAT_LS64. - Add a feature check to check for the existing four variants of the LS64 feature and detect future extensions. - Add code to save and restore the ACCDATA_EL1 register on secure/non-secure context switches. - Enable the feature with runtime detection for FVP and Arm FPGA. Please note that the *basic* FEAT_LS64 feature does not feature any trap bits, it's only the addition of the ACCDATA_EL1 system register that adds these traps and the SCR_EL3 bits. Change-Id: Ie3e2ca2d9c4fbbd45c0cc6089accbb825579138a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
325 lines
7.9 KiB
C
325 lines
7.9 KiB
C
/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CONTEXT_EL1_H
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#define CONTEXT_EL1_H
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#include <lib/extensions/sysreg128.h>
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#ifndef __ASSEMBLER__
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/*******************************************************************************
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* EL1 Registers:
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* AArch64 EL1 system register context structure for preserving the
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* architectural state during world switches.
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******************************************************************************/
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typedef struct el1_common_regs {
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uint64_t spsr_el1;
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uint64_t elr_el1;
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#if (!ERRATA_SPECULATIVE_AT)
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uint64_t sctlr_el1;
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uint64_t tcr_el1;
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#endif /* ERRATA_SPECULATIVE_AT=0 */
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uint64_t cpacr_el1;
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uint64_t csselr_el1;
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uint64_t sp_el1;
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uint64_t esr_el1;
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uint64_t mair_el1;
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uint64_t amair_el1;
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uint64_t actlr_el1;
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uint64_t tpidr_el1;
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uint64_t tpidr_el0;
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uint64_t tpidrro_el0;
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uint64_t far_el1;
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uint64_t afsr0_el1;
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uint64_t afsr1_el1;
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uint64_t contextidr_el1;
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uint64_t vbar_el1;
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uint64_t mdccint_el1;
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uint64_t mdscr_el1;
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sysreg_t par_el1;
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sysreg_t ttbr0_el1;
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sysreg_t ttbr1_el1;
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} el1_common_regs_t;
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typedef struct el1_aarch32_regs {
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uint64_t spsr_abt;
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uint64_t spsr_und;
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uint64_t spsr_irq;
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uint64_t spsr_fiq;
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uint64_t dacr32_el2;
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uint64_t ifsr32_el2;
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} el1_aarch32_regs_t;
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typedef struct el1_arch_timer_regs {
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uint64_t cntp_ctl_el0;
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uint64_t cntp_cval_el0;
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uint64_t cntv_ctl_el0;
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uint64_t cntv_cval_el0;
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uint64_t cntkctl_el1;
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} el1_arch_timer_regs_t;
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typedef struct el1_mte2_regs {
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uint64_t tfsre0_el1;
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uint64_t tfsr_el1;
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uint64_t rgsr_el1;
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uint64_t gcr_el1;
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} el1_mte2_regs_t;
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typedef struct el1_ras_regs {
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uint64_t disr_el1;
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} el1_ras_regs_t;
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typedef struct el1_s1pie_regs {
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uint64_t pire0_el1;
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uint64_t pir_el1;
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} el1_s1pie_regs_t;
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typedef struct el1_s1poe_regs {
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uint64_t por_el1;
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} el1_s1poe_regs_t;
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typedef struct el1_s2poe_regs {
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uint64_t s2por_el1;
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} el1_s2poe_regs_t;
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typedef struct el1_tcr2_regs {
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uint64_t tcr2_el1;
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} el1_tcr2_regs_t;
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typedef struct el1_trf_regs {
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uint64_t trfcr_el1;
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} el1_trf_regs_t;
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typedef struct el1_csv2_2_regs {
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uint64_t scxtnum_el0;
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uint64_t scxtnum_el1;
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} el1_csv2_2_regs_t;
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typedef struct el1_gcs_regs {
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uint64_t gcscr_el1;
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uint64_t gcscre0_el1;
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uint64_t gcspr_el1;
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uint64_t gcspr_el0;
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} el1_gcs_regs_t;
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typedef struct el1_the_regs {
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sysreg_t rcwmask_el1;
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sysreg_t rcwsmask_el1;
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} el1_the_regs_t;
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typedef struct el1_sctlr2_regs {
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uint64_t sctlr2_el1;
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} el1_sctlr2_regs_t;
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typedef struct el1_ls64_regs {
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uint64_t accdata_el1;
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} el1_ls64_regs_t;
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typedef struct el1_sysregs {
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el1_common_regs_t common;
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#if CTX_INCLUDE_AARCH32_REGS
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el1_aarch32_regs_t el1_aarch32;
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#endif
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#if NS_TIMER_SWITCH
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el1_arch_timer_regs_t arch_timer;
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#endif
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#if ENABLE_FEAT_MTE2
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el1_mte2_regs_t mte2;
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#endif
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#if ENABLE_FEAT_RAS
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el1_ras_regs_t ras;
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#endif
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#if ENABLE_FEAT_S1PIE
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el1_s1pie_regs_t s1pie;
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#endif
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#if ENABLE_FEAT_S1POE
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el1_s1poe_regs_t s1poe;
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#endif
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#if ENABLE_FEAT_S2POE
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el1_s2poe_regs_t s2poe;
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#endif
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#if ENABLE_FEAT_TCR2
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el1_tcr2_regs_t tcr2;
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#endif
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#if ENABLE_TRF_FOR_NS
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el1_trf_regs_t trf;
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#endif
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#if ENABLE_FEAT_CSV2_2
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el1_csv2_2_regs_t csv2_2;
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#endif
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#if ENABLE_FEAT_GCS
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el1_gcs_regs_t gcs;
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#endif
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#if ENABLE_FEAT_THE
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el1_the_regs_t the;
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#endif
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#if ENABLE_FEAT_SCTLR2
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el1_sctlr2_regs_t sctlr2;
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#endif
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#if ENABLE_FEAT_LS64_ACCDATA
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el1_ls64_regs_t ls64;
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#endif
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} el1_sysregs_t;
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/*
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* Macros to access members related to individual features of the el1_sysregs_t
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* structures.
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*/
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#define read_el1_ctx_common(ctx, reg) (((ctx)->common).reg)
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#define write_el1_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \
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= (uint64_t) (val))
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#if NS_TIMER_SWITCH
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#define read_el1_ctx_arch_timer(ctx, reg) (((ctx)->arch_timer).reg)
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#define write_el1_ctx_arch_timer(ctx, reg, val) ((((ctx)->arch_timer).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_arch_timer(ctx, reg) ULL(0)
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#define write_el1_ctx_arch_timer(ctx, reg, val)
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#endif /* NS_TIMER_SWITCH */
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#if CTX_INCLUDE_AARCH32_REGS
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#define read_el1_ctx_aarch32(ctx, reg) (((ctx)->el1_aarch32).reg)
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#define write_el1_ctx_aarch32(ctx, reg, val) ((((ctx)->el1_aarch32).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_aarch32(ctx, reg) ULL(0)
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#define write_el1_ctx_aarch32(ctx, reg, val)
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#endif /* CTX_INCLUDE_AARCH32_REGS */
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#if ENABLE_FEAT_MTE2
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#define read_el1_ctx_mte2(ctx, reg) (((ctx)->mte2).reg)
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#define write_el1_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_mte2(ctx, reg) ULL(0)
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#define write_el1_ctx_mte2(ctx, reg, val)
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#endif /* ENABLE_FEAT_MTE2 */
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#if ENABLE_FEAT_RAS
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#define read_el1_ctx_ras(ctx, reg) (((ctx)->ras).reg)
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#define write_el1_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_ras(ctx, reg) ULL(0)
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#define write_el1_ctx_ras(ctx, reg, val)
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#endif /* ENABLE_FEAT_RAS */
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#if ENABLE_FEAT_S1PIE
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#define read_el1_ctx_s1pie(ctx, reg) (((ctx)->s1pie).reg)
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#define write_el1_ctx_s1pie(ctx, reg, val) ((((ctx)->s1pie).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_s1pie(ctx, reg) ULL(0)
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#define write_el1_ctx_s1pie(ctx, reg, val)
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#endif /* ENABLE_FEAT_S1PIE */
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#if ENABLE_FEAT_S1POE
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#define read_el1_ctx_s1poe(ctx, reg) (((ctx)->s1poe).reg)
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#define write_el1_ctx_s1poe(ctx, reg, val) ((((ctx)->s1poe).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_s1poe(ctx, reg) ULL(0)
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#define write_el1_ctx_s1poe(ctx, reg, val)
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#endif /* ENABLE_FEAT_S1POE */
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#if ENABLE_FEAT_S2POE
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#define read_el1_ctx_s2poe(ctx, reg) (((ctx)->s2poe).reg)
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#define write_el1_ctx_s2poe(ctx, reg, val) ((((ctx)->s2poe).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_s2poe(ctx, reg) ULL(0)
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#define write_el1_ctx_s2poe(ctx, reg, val)
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#endif /* ENABLE_FEAT_S2POE */
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#if ENABLE_FEAT_TCR2
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#define read_el1_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg)
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#define write_el1_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_tcr2(ctx, reg) ULL(0)
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#define write_el1_ctx_tcr2(ctx, reg, val)
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#endif /* ENABLE_FEAT_TCR2 */
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#if ENABLE_TRF_FOR_NS
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#define read_el1_ctx_trf(ctx, reg) (((ctx)->trf).reg)
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#define write_el1_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_trf(ctx, reg) ULL(0)
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#define write_el1_ctx_trf(ctx, reg, val)
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#endif /* ENABLE_TRF_FOR_NS */
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#if ENABLE_FEAT_CSV2_2
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#define read_el1_ctx_csv2_2(ctx, reg) (((ctx)->csv2_2).reg)
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#define write_el1_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2_2).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_csv2_2(ctx, reg) ULL(0)
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#define write_el1_ctx_csv2_2(ctx, reg, val)
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#endif /* ENABLE_FEAT_CSV2_2 */
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#if ENABLE_FEAT_GCS
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#define read_el1_ctx_gcs(ctx, reg) (((ctx)->gcs).reg)
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#define write_el1_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_gcs(ctx, reg) ULL(0)
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#define write_el1_ctx_gcs(ctx, reg, val)
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#endif /* ENABLE_FEAT_GCS */
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#if ENABLE_FEAT_THE
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#define read_el1_ctx_the(ctx, reg) (((ctx)->the).reg)
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#define write_el1_ctx_the(ctx, reg, val) ((((ctx)->the).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_the(ctx, reg) ULL(0)
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#define write_el1_ctx_the(ctx, reg, val)
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#endif /* ENABLE_FEAT_THE */
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#if ENABLE_FEAT_SCTLR2
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#define read_el1_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg)
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#define write_el1_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_sctlr2(ctx, reg) ULL(0)
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#define write_el1_ctx_sctlr2(ctx, reg, val)
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#endif /* ENABLE_FEAT_SCTLR2 */
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#if ENABLE_FEAT_LS64_ACCDATA
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#define read_el1_ctx_ls64(ctx, reg) (((ctx)->ls64).reg)
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#define write_el1_ctx_ls64(ctx, reg, val) ((((ctx)->ls64).reg) \
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= (uint64_t) (val))
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#else
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#define read_el1_ctx_ls64(ctx, reg) ULL(0)
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#define write_el1_ctx_ls64(ctx, reg, val)
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#endif /* ENABLE_FEAT_LS64_ACCDATA */
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/******************************************************************************/
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#endif /* __ASSEMBLER__ */
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#endif /* CONTEXT_EL1_H */
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