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e2a65959bc
MT8173 platform code is incompatible with RESET_TO_BL31, add #error directive to prevent the case. We also move mt8173_def.h and plat_private.h to include directory, and remove some unnecessary code. Change-Id: I47b8d0a506820a4ea1fbe8c8fb0ec6c68d88feb5 Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
130 lines
5.2 KiB
C
130 lines
5.2 KiB
C
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#if IMAGE_BL1
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#define PLATFORM_STACK_SIZE 0x440
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#elif IMAGE_BL2
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#define PLATFORM_STACK_SIZE 0x400
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#elif IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x800
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#elif IMAGE_BL32
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#define PLATFORM_STACK_SIZE 0x440
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#endif
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
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#define PLATFORM_SYSTEM_COUNT 1
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#define PLATFORM_CLUSTER_COUNT 2
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#define PLATFORM_CLUSTER0_CORE_COUNT 4
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#define PLATFORM_CLUSTER1_CORE_COUNT 2
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
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#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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/*
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* MT8173 SRAM memory layout
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* 0x100000 +-------------------+
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* | shared mem (4KB) |
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* 0x101000 +-------------------+
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* | |
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* | BL3-1 (124KB) |
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* | |
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* 0x120000 +-------------------+
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* | reserved (64KB) |
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* 0x130000 +-------------------+
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*/
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/* TF txet, ro, rw, xlat table, coherent memory ... etc.
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* Size: release: 128KB, debug: 128KB
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*/
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#define TZRAM_BASE (0x100000)
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#if DEBUG
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#define TZRAM_SIZE (0x20000)
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#else
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#define TZRAM_SIZE (0x20000)
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#endif
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/* Reserved: 64KB */
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#define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE)
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#define TZRAM2_SIZE (0x10000)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
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* little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + 0x1000)
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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#define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 4
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* __PLATFORM_DEF_H__ */
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