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195381a913
About a year ago there was a change in the underlying Arm platform design framework, which lead to a reorganisation of the interrupt map (to make room for multi-chip designs). This lead to the PL011 debug UART interrupt to move from SPI 115 to SPI 415. Unfortunately there is not a good or easy way to auto-detect this change: Flooding the TX FIFO and checking GICD_ISPENDR registers might be possible, but sounds a bit over the top for BL31. So we would need to break one group of images: newer ones, as we do right now, or older ones. By now every interesting FPGA image seems to use the newer IRQ, so in the interest of having a smooth experience for most users, lets switch to this IRQ. When people are interested in older images, they can either change the number back in the .dts file, or provide a patched DTB on the FPGA command line. Change-Id: I3c7e7b711f5142813bd94eecde3095a4fc555bb3 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
102 lines
2.5 KiB
Text
102 lines
2.5 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* Devicetree for the Arm Ltd. FPGA platform
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* Number and kind of CPU cores differs from image to image, so the
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* topology is auto-detected by BL31, and the /cpus node is created and
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* populated accordingly at runtime.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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model = "ARM FPGA";
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compatible = "arm,fpga", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &dbg_uart;
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};
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chosen {
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stdout-path = "serial0:38400n8";
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bootargs = "console=ttyAMA0,38400n8 earlycon";
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/* Allow to upload a generous 100MB initrd payload. */
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linux,initrd-start = <0x0 0x84000000>;
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linux,initrd-end = <0x0 0x8a400000>;
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};
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/* /cpus node will be added by BL31 at runtime. */
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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clock-frequency = <10000000>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* This node will be removed at runtime on cores without SPE. */
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spe-pmu {
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compatible = "arm,statistical-profiling-extension-v1";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x80000000>,
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<0x8 0x80000000 0x1 0x80000000>;
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};
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bus_refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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uartclk: baudclock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <10000000>;
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clock-output-names = "uartclk";
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};
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dbg_uart: serial@7ff80000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x7ff80000 0x0 0x00001000>;
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interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&bus_refclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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gic: interrupt-controller@30000000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0x0 0x00010000>, /* GICD */
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/* The GICR size will be adjusted at runtime to match the cores. */
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<0x0 0x30040000 0x0 0x00020000>; /* GICR for one core */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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