mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
1300bbce15
Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. If an interrupt is a PPI, and the node pointed in the 4th cell must be a subnode of the "ppi-partitions" in the GIC node. For interrupt types other than PPI, this cell must be zero. This is a preparison for sequential changes for interrupt partitions, as the first step, it sets all zeros for the interrupt affinity. Change-Id: I66490a86a27aad5db6b1a42c2d8e0d042eee46a9 Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com> Signed-off-by: Leo Yan <leo.yan@arm.com>
84 lines
2 KiB
Text
84 lines
2 KiB
Text
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define GIC_CTRL_ADDR 2c010000
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#define GIC_GICR_OFFSET 0x200000
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#define UART_OFFSET 0x1000
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#ifdef TC_RESOLUTION_1920X1080P60
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#define VENCODER_TIMING_CLK 148500000
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#define VENCODER_TIMING \
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clock-frequency = <VENCODER_TIMING_CLK>; \
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hactive = <1920>; \
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vactive = <1080>; \
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hfront-porch = <88>; \
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hback-porch = <148>; \
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hsync-len = <44>; \
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vfront-porch = <4>; \
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vback-porch = <36>; \
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vsync-len = <5>
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#else /* TC_RESOLUTION_640X480P60 */
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#define VENCODER_TIMING_CLK 25175000
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#define VENCODER_TIMING \
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clock-frequency = <VENCODER_TIMING_CLK>; \
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hactive = <640>; \
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vactive = <480>; \
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hfront-porch = <16>; \
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hback-porch = <48>; \
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hsync-len = <96>; \
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vfront-porch = <10>; \
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vback-porch = <33>; \
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vsync-len = <2>
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#endif
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/ {
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chosen {
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stdout-path = "serial0:115200n8";
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};
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ethernet: ethernet@18000000 {
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compatible = "smsc,lan91c111";
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};
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mmci: mmci@1c050000 {
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cd-gpios = <&sysreg 0 0>;
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};
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rtc@1c170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x0 0x1C170000 0x0 0x1000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&soc_refclk>;
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clock-names = "apb_pclk";
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};
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kmi@1c060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c060000 0x0 0x1000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c070000 0x0 0x1000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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virtio_block@1c130000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c130000 0x0 0x200>;
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/* spec lists this wrong */
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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};
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