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17e84eedb2
- Interrupt configuration is a 2-bit field, so the field shift has to
be double that of the bit number.
- Interrupt configuration (level- or edge-trigger) is specified in the
MSB of the field, not LSB.
Fixes applied to both GICv2 and GICv3 drivers.
Fixes ARM-software/tf-issues#570
Change-Id: Ia6ae6ed9ba9fb0e3eb0f921a833af48e365ba359
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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||
|---|---|---|
| .. | ||
| cci | ||
| cci400 | ||
| ccn | ||
| gic | ||
| pl011 | ||
| pl061 | ||
| smmu | ||
| sp804 | ||
| sp805 | ||
| tzc | ||
| tzc400 | ||