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https://github.com/ARM-software/arm-trusted-firmware.git
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179a130aea
GPIOs are configured as secure by default on STM32MP2. The former code is then put under #if STM32MP13 || STM32MP15. The else part is for STM32MP2 family. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Change-Id: I80c5944d4ae662f9e28269c3dc543b13f0e26a7b
398 lines
9.8 KiB
C
398 lines
9.8 KiB
C
/*
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* Copyright (c) 2016-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/clk.h>
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#include <drivers/st/stm32_gpio.h>
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#include <drivers/st/stm32mp_clkfunc.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#define DT_GPIO_BANK_SHIFT 12
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#define DT_GPIO_BANK_MASK GENMASK(16, 12)
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#define DT_GPIO_PIN_SHIFT 8
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#define DT_GPIO_PIN_MASK GENMASK(11, 8)
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#define DT_GPIO_MODE_MASK GENMASK(7, 0)
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static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type,
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uint32_t speed, uint32_t pull, uint32_t od,
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uint32_t alternate, uint8_t status);
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/*******************************************************************************
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* This function gets GPIO bank node in DT.
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* Returns node offset if status is okay in DT, else return 0
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******************************************************************************/
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static int ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node)
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{
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int pinctrl_subnode;
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uint32_t bank_offset = stm32_get_gpio_bank_offset(bank);
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fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) {
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const fdt32_t *cuint;
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if (fdt_getprop(fdt, pinctrl_subnode,
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"gpio-controller", NULL) == NULL) {
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continue;
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}
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cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL);
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if (cuint == NULL) {
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continue;
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}
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if ((fdt32_to_cpu(*cuint) == bank_offset) &&
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(fdt_get_status(pinctrl_subnode) != DT_DISABLED)) {
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return pinctrl_subnode;
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}
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}
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return 0;
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}
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/*******************************************************************************
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* This function gets the pin settings from DT information.
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* When analyze and parsing is done, set the GPIO registers.
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* Returns 0 on success and a negative FDT error code on failure.
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******************************************************************************/
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static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
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{
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const fdt32_t *cuint, *slewrate;
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int len;
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int pinctrl_node;
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uint32_t i;
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uint32_t speed = GPIO_SPEED_LOW;
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uint32_t pull = GPIO_NO_PULL;
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cuint = fdt_getprop(fdt, node, "pinmux", &len);
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if (cuint == NULL) {
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return -FDT_ERR_NOTFOUND;
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}
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pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node));
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if (pinctrl_node < 0) {
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return -FDT_ERR_NOTFOUND;
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}
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slewrate = fdt_getprop(fdt, node, "slew-rate", NULL);
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if (slewrate != NULL) {
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speed = fdt32_to_cpu(*slewrate);
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}
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if (fdt_getprop(fdt, node, "bias-pull-up", NULL) != NULL) {
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pull = GPIO_PULL_UP;
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} else if (fdt_getprop(fdt, node, "bias-pull-down", NULL) != NULL) {
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pull = GPIO_PULL_DOWN;
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} else {
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VERBOSE("No bias configured in node %d\n", node);
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}
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for (i = 0U; i < ((uint32_t)len / sizeof(uint32_t)); i++) {
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uint32_t pincfg;
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uint32_t bank;
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uint32_t pin;
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uint32_t mode;
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uint32_t alternate = GPIO_ALTERNATE_(0);
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uint32_t type;
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uint32_t od = GPIO_OD_OUTPUT_LOW;
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int bank_node;
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int clk;
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pincfg = fdt32_to_cpu(*cuint);
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cuint++;
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bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT;
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pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT;
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mode = pincfg & DT_GPIO_MODE_MASK;
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switch (mode) {
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case 0:
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mode = GPIO_MODE_INPUT;
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break;
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case 1 ... 16:
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alternate = mode - 1U;
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mode = GPIO_MODE_ALTERNATE;
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break;
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case 17:
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mode = GPIO_MODE_ANALOG;
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break;
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default:
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mode = GPIO_MODE_OUTPUT;
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break;
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}
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if (fdt_getprop(fdt, node, "drive-open-drain", NULL) != NULL) {
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type = GPIO_TYPE_OPEN_DRAIN;
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} else {
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type = GPIO_TYPE_PUSH_PULL;
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}
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if (fdt_getprop(fdt, node, "output-high", NULL) != NULL) {
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if (mode == GPIO_MODE_INPUT) {
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mode = GPIO_MODE_OUTPUT;
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od = GPIO_OD_OUTPUT_HIGH;
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}
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}
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if (fdt_getprop(fdt, node, "output-low", NULL) != NULL) {
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if (mode == GPIO_MODE_INPUT) {
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mode = GPIO_MODE_OUTPUT;
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od = GPIO_OD_OUTPUT_LOW;
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}
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}
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bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node);
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if (bank_node == 0) {
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ERROR("PINCTRL inconsistent in DT\n");
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panic();
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}
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clk = fdt_get_clock_id(bank_node);
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if (clk < 0) {
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return -FDT_ERR_NOTFOUND;
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}
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/* Platform knows the clock: assert it is okay */
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assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank));
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set_gpio(bank, pin, mode, type, speed, pull, od, alternate, status);
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}
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return 0;
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}
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/*******************************************************************************
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* This function gets the pin settings from DT information.
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* When analyze and parsing is done, set the GPIO registers.
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* Returns 0 on success and a negative FDT/ERRNO error code on failure.
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******************************************************************************/
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int dt_set_pinctrl_config(int node)
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{
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const fdt32_t *cuint;
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int lenp;
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uint32_t i;
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uint8_t status;
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void *fdt;
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if (fdt_get_address(&fdt) == 0) {
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return -FDT_ERR_NOTFOUND;
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}
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status = fdt_get_status(node);
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if (status == DT_DISABLED) {
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return -FDT_ERR_NOTFOUND;
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}
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cuint = fdt_getprop(fdt, node, "pinctrl-0", &lenp);
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if (cuint == NULL) {
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return -FDT_ERR_NOTFOUND;
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}
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for (i = 0; i < ((uint32_t)lenp / 4U); i++) {
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int p_node, p_subnode;
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p_node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
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if (p_node < 0) {
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return -FDT_ERR_NOTFOUND;
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}
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fdt_for_each_subnode(p_subnode, fdt, p_node) {
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int ret = dt_set_gpio_config(fdt, p_subnode, status);
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if (ret < 0) {
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return ret;
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}
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}
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cuint++;
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}
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return 0;
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}
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static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type,
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uint32_t speed, uint32_t pull, uint32_t od,
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uint32_t alternate, uint8_t status)
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{
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uintptr_t base = stm32_get_gpio_bank_base(bank);
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unsigned long clock = stm32_get_gpio_bank_clock(bank);
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assert(pin <= GPIO_PIN_MAX);
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clk_enable(clock);
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mmio_clrsetbits_32(base + GPIO_MODE_OFFSET,
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(uint32_t)GPIO_MODE_MASK << (pin << 1U),
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mode << (pin << 1U));
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mmio_clrsetbits_32(base + GPIO_TYPE_OFFSET,
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(uint32_t)GPIO_TYPE_MASK << pin,
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type << pin);
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mmio_clrsetbits_32(base + GPIO_SPEED_OFFSET,
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(uint32_t)GPIO_SPEED_MASK << (pin << 1U),
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speed << (pin << 1U));
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mmio_clrsetbits_32(base + GPIO_PUPD_OFFSET,
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(uint32_t)GPIO_PULL_MASK << (pin << 1U),
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pull << (pin << 1U));
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if (pin < GPIO_ALT_LOWER_LIMIT) {
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mmio_clrsetbits_32(base + GPIO_AFRL_OFFSET,
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(uint32_t)GPIO_ALTERNATE_MASK << (pin << 2U),
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alternate << (pin << 2U));
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} else {
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uint32_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2U;
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mmio_clrsetbits_32(base + GPIO_AFRH_OFFSET,
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(uint32_t)GPIO_ALTERNATE_MASK << shift,
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alternate << shift);
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}
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mmio_clrsetbits_32(base + GPIO_OD_OFFSET,
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(uint32_t)GPIO_OD_MASK << pin,
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od << pin);
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VERBOSE("GPIO %u mode set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_MODE_OFFSET));
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VERBOSE("GPIO %u type set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_TYPE_OFFSET));
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VERBOSE("GPIO %u speed set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_SPEED_OFFSET));
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VERBOSE("GPIO %u mode pull to 0x%x\n", bank,
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mmio_read_32(base + GPIO_PUPD_OFFSET));
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VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank,
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mmio_read_32(base + GPIO_AFRL_OFFSET));
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VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
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mmio_read_32(base + GPIO_AFRH_OFFSET));
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VERBOSE("GPIO %u output data set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_OD_OFFSET));
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clk_disable(clock);
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#if STM32MP13 || STM32MP15
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if (status == DT_SECURE) {
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stm32mp_register_secure_gpio(bank, pin);
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#if !IMAGE_BL2
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set_gpio_secure_cfg(bank, pin, true);
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#endif
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} else {
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stm32mp_register_non_secure_gpio(bank, pin);
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#if !IMAGE_BL2
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set_gpio_secure_cfg(bank, pin, false);
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#endif
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}
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#else /* !STM32MP13 && !STM32MP15 */
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set_gpio_secure_cfg(bank, pin, true);
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#endif /* STM32MP13 || STM32MP15 */
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}
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void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
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{
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uintptr_t base = stm32_get_gpio_bank_base(bank);
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unsigned long clock = stm32_get_gpio_bank_clock(bank);
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assert(pin <= GPIO_PIN_MAX);
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clk_enable(clock);
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if (secure) {
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mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
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} else {
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mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
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}
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clk_disable(clock);
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}
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void set_gpio_reset_cfg(uint32_t bank, uint32_t pin)
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{
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set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_TYPE_PUSH_PULL,
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GPIO_SPEED_LOW, GPIO_NO_PULL, GPIO_OD_OUTPUT_LOW,
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GPIO_ALTERNATE_(0), DT_DISABLED);
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set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank));
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}
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void set_gpio_level(uint32_t bank, uint32_t pin, enum gpio_level level)
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{
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uintptr_t base = stm32_get_gpio_bank_base(bank);
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unsigned long clock = stm32_get_gpio_bank_clock(bank);
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assert(pin <= GPIO_PIN_MAX);
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clk_enable(clock);
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if (level == GPIO_LEVEL_HIGH) {
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mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin));
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} else {
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mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin + 16U));
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}
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VERBOSE("GPIO %u level set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_IDR_OFFSET));
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clk_disable(clock);
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}
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enum gpio_level get_gpio_level(uint32_t bank, uint32_t pin)
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{
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uintptr_t base = stm32_get_gpio_bank_base(bank);
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unsigned long clock = stm32_get_gpio_bank_clock(bank);
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enum gpio_level level = GPIO_LEVEL_LOW;
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assert(pin <= GPIO_PIN_MAX);
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clk_enable(clock);
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if (mmio_read_32(base + GPIO_IDR_OFFSET) & BIT(pin)) {
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level = GPIO_LEVEL_HIGH;
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}
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VERBOSE("GPIO %u get level 0x%x\n", bank,
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mmio_read_32(base + GPIO_IDR_OFFSET));
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clk_disable(clock);
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return level;
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}
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void set_gpio_config(uint32_t bank, uint32_t pin, uint32_t config, uint8_t status)
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{
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uint32_t mode = GPIO_MODE_OUTPUT;
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uint32_t od = 0U;
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uint32_t pull = GPIO_NO_PULL;
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VERBOSE("GPIO %u:%u set config to 0x%x\n", bank, pin, config);
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if (config & GPIOF_DIR_IN) {
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mode = GPIO_MODE_INPUT;
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}
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if (config & GPIOF_OUT_INIT_HIGH) {
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od = 1U;
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}
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if (config & GPIOF_PULL_UP) {
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pull |= GPIO_PULL_UP;
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}
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if (config & GPIOF_PULL_DOWN) {
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pull |= GPIO_PULL_DOWN;
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}
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set_gpio(bank, pin, mode, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_LOW,
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pull, od, GPIO_ALTERNATE_(0), status);
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}
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