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https://github.com/ARM-software/arm-trusted-firmware.git
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1483b3c3d2
It was only used for an error trace, with little added value. This allows some gains in DDR driver data size. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I02e2fc75efd90ff188e62f39850b9bd4c3af1649
97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/*
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* Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32mp_ddr.h>
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#include <drivers/st/stm32mp_ddrctrl_regs.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#define INVALID_OFFSET 0xFFU
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static uintptr_t get_base_addr(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_base_type base)
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{
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if (base == DDRPHY_BASE) {
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return (uintptr_t)priv->phy;
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} else {
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return (uintptr_t)priv->ctl;
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}
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}
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void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type,
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const void *param, const struct stm32mp_ddr_reg_info *ddr_registers)
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{
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unsigned int i;
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unsigned int value;
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enum stm32mp_ddr_base_type base = ddr_registers[type].base;
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uintptr_t base_addr = get_base_addr(priv, base);
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const struct stm32mp_ddr_reg_desc *desc = ddr_registers[type].desc;
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VERBOSE("init %s\n", ddr_registers[type].name);
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for (i = 0; i < ddr_registers[type].size; i++) {
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uintptr_t ptr = base_addr + desc[i].offset;
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if (desc[i].par_offset == INVALID_OFFSET) {
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ERROR("invalid parameter offset for %s - index %u",
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ddr_registers[type].name, i);
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panic();
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} else {
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value = *((uint32_t *)((uintptr_t)param +
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desc[i].par_offset));
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mmio_write_32(ptr, value);
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}
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}
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}
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/* Start quasi dynamic register update */
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void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl)
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{
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mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
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VERBOSE("[0x%lx] swctl = 0x%x\n",
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(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
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}
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/* Wait quasi dynamic register update */
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void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl)
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{
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uint64_t timeout;
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uint32_t swstat;
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mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
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VERBOSE("[0x%lx] swctl = 0x%x\n",
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(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
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timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
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do {
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swstat = mmio_read_32((uintptr_t)&ctl->swstat);
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VERBOSE("[0x%lx] swstat = 0x%x ",
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(uintptr_t)&ctl->swstat, swstat);
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if (timeout_elapsed(timeout)) {
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panic();
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}
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} while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U);
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VERBOSE("[0x%lx] swstat = 0x%x\n",
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(uintptr_t)&ctl->swstat, swstat);
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}
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void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl)
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{
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/* Enable uMCTL2 AXI port 0 */
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mmio_setbits_32((uintptr_t)&ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
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VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", (uintptr_t)&ctl->pctrl_0,
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mmio_read_32((uintptr_t)&ctl->pctrl_0));
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#if STM32MP_DDR_DUAL_AXI_PORT
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/* Enable uMCTL2 AXI port 1 */
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mmio_setbits_32((uintptr_t)&ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
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VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1,
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mmio_read_32((uintptr_t)&ctl->pctrl_1));
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#endif
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}
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