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https://github.com/ARM-software/arm-trusted-firmware.git
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10bcd76157
The errata reporting policy is as follows:
- If an errata workaround is enabled:
- If it applies (i.e. the CPU is affected by the errata), an INFO
message is printed, confirming that the errata workaround has been
applied.
- If it does not apply, a VERBOSE message is printed, confirming
that the errata workaround has been skipped.
- If an errata workaround is not enabled, but would have applied had
it been, a WARN message is printed, alerting that errata workaround
is missing.
The CPU errata messages are printed by both BL1 (primary CPU only) and
runtime firmware on debug builds, once for each CPU/errata combination.
Relevant output from Juno r1 console when ARM Trusted Firmware is built
with PLAT=juno LOG_LEVEL=50 DEBUG=1:
VERBOSE: BL1: cortex_a57: errata workaround for 806969 was not applied
VERBOSE: BL1: cortex_a57: errata workaround for 813420 was not applied
INFO: BL1: cortex_a57: errata workaround for disable_ldnp_overread was applied
WARNING: BL1: cortex_a57: errata workaround for 826974 was missing!
WARNING: BL1: cortex_a57: errata workaround for 826977 was missing!
WARNING: BL1: cortex_a57: errata workaround for 828024 was missing!
WARNING: BL1: cortex_a57: errata workaround for 829520 was missing!
WARNING: BL1: cortex_a57: errata workaround for 833471 was missing!
...
VERBOSE: BL31: cortex_a57: errata workaround for 806969 was not applied
VERBOSE: BL31: cortex_a57: errata workaround for 813420 was not applied
INFO: BL31: cortex_a57: errata workaround for disable_ldnp_overread was applied
WARNING: BL31: cortex_a57: errata workaround for 826974 was missing!
WARNING: BL31: cortex_a57: errata workaround for 826977 was missing!
WARNING: BL31: cortex_a57: errata workaround for 828024 was missing!
WARNING: BL31: cortex_a57: errata workaround for 829520 was missing!
WARNING: BL31: cortex_a57: errata workaround for 833471 was missing!
...
VERBOSE: BL31: cortex_a53: errata workaround for 826319 was not applied
INFO: BL31: cortex_a53: errata workaround for disable_non_temporal_hint was applied
Also update documentation.
Change-Id: Iccf059d3348adb876ca121cdf5207bdbbacf2aba
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
251 lines
6.9 KiB
ArmAsm
251 lines
6.9 KiB
ArmAsm
/*
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_MACROS_S__
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#define __CPU_MACROS_S__
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#include <arch.h>
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#include <errata_report.h>
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#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
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(MIDR_PN_MASK << MIDR_PN_SHIFT)
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/* The number of CPU operations allowed */
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#define CPU_MAX_PWR_DWN_OPS 2
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/* Special constant to specify that CPU has no reset function */
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#define CPU_NO_RESET_FUNC 0
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/* Word size for 64-bit CPUs */
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#define CPU_WORD_SIZE 8
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/*
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* Whether errata status needs reporting. Errata status is printed in debug
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* builds for both BL1 and BL31 images.
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*/
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#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG
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# define REPORT_ERRATA 1
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#else
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# define REPORT_ERRATA 0
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#endif
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/*
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* Define the offsets to the fields in cpu_ops structure.
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*/
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.struct 0
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CPU_MIDR: /* cpu_ops midr */
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.space 8
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/* Reset fn is needed in BL at reset vector */
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#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
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CPU_RESET_FUNC: /* cpu_ops reset_func */
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.space 8
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#endif
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#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
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CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
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.space (8 * CPU_MAX_PWR_DWN_OPS)
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#endif
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/*
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* Fields required to print errata status. Only in BL31 that the printing
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* require mutual exclusion and printed flag.
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*/
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#if REPORT_ERRATA
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CPU_ERRATA_FUNC:
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.space 8
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#ifdef IMAGE_BL31
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CPU_ERRATA_LOCK:
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.space 8
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CPU_ERRATA_PRINTED:
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.space 8
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#endif
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#endif
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#if defined(IMAGE_BL31) && CRASH_REPORTING
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CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
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.space 8
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#endif
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CPU_OPS_SIZE = .
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/*
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* Write given expressions as quad words
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*
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* _count:
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* Write at least _count quad words. If the given number of
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* expressions is less than _count, repeat the last expression to
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* fill _count quad words in total
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* _rest:
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* Optional list of expressions. _this is for parameter extraction
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* only, and has no significance to the caller
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*
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* Invoked as:
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* fill_constants 2, foo, bar, blah, ...
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*/
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.macro fill_constants _count:req, _this, _rest:vararg
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.ifgt \_count
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/* Write the current expression */
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.ifb \_this
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.error "Nothing to fill"
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.endif
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.quad \_this
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/* Invoke recursively for remaining expressions */
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.ifnb \_rest
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fill_constants \_count-1, \_rest
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.else
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fill_constants \_count-1, \_this
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.endif
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.endif
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.endm
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/*
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* Declare CPU operations
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*
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* _name:
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* Name of the CPU for which operations are being specified
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* _midr:
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* Numeric value expected to read from CPU's MIDR
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* _resetfunc:
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* Reset function for the CPU. If there's no CPU reset function,
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* specify CPU_NO_RESET_FUNC
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* _power_down_ops:
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* Comma-separated list of functions to perform power-down
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* operatios on the CPU. At least one, and up to
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* CPU_MAX_PWR_DWN_OPS number of functions may be specified.
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* Starting at power level 0, these functions shall handle power
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* down at subsequent power levels. If there aren't exactly
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* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
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* used to handle power down at subsequent levels
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*/
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.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
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_power_down_ops:vararg
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.section cpu_ops, "a"
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.align 3
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.type cpu_ops_\_name, %object
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.quad \_midr
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#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
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.quad \_resetfunc
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#endif
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#ifdef IMAGE_BL31
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1:
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/* Insert list of functions */
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fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
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2:
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/*
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* Error if no or more than CPU_MAX_PWR_DWN_OPS were specified in the
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* list
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*/
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.ifeq 2b - 1b
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.error "At least one power down function must be specified"
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.else
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.iflt 2b - 1b - (CPU_MAX_PWR_DWN_OPS * CPU_WORD_SIZE)
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.error "More than CPU_MAX_PWR_DWN_OPS functions specified"
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.endif
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.endif
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#endif
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#if REPORT_ERRATA
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.ifndef \_name\()_cpu_str
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/*
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* Place errata reported flag, and the spinlock to arbitrate access to
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* it in the data section.
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*/
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.pushsection .data
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define_asm_spinlock \_name\()_errata_lock
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\_name\()_errata_reported:
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.word 0
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.popsection
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/* Place CPU string in rodata */
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.pushsection .rodata
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\_name\()_cpu_str:
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.asciz "\_name"
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.popsection
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.endif
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/*
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* Weakly-bound, optional errata status printing function for CPUs of
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* this class.
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*/
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.weak \_name\()_errata_report
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.quad \_name\()_errata_report
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#ifdef IMAGE_BL31
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/* Pointers to errata lock and reported flag */
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.quad \_name\()_errata_lock
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.quad \_name\()_errata_reported
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#endif
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#endif
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#if defined(IMAGE_BL31) && CRASH_REPORTING
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.quad \_name\()_cpu_reg_dump
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#endif
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.endm
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#if REPORT_ERRATA
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/*
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* Print status of a CPU errata
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*
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* _chosen:
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* Identifier indicating whether or not a CPU errata has been
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* compiled in.
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* _cpu:
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* Name of the CPU
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* _id:
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* Errata identifier
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* _rev_var:
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* Register containing the combined value CPU revision and variant
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* - typically the return value of cpu_get_rev_var
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*/
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.macro report_errata _chosen, _cpu, _id, _rev_var=x8
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/* Stash a string with errata ID */
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.pushsection .rodata
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\_cpu\()_errata_\_id\()_str:
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.asciz "\_id"
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.popsection
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/* Check whether errata applies */
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mov x0, \_rev_var
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bl check_errata_\_id
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.ifeq \_chosen
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/*
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* Errata workaround has not been compiled in. If the errata would have
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* applied had it been compiled in, print its status as missing.
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*/
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cbz x0, 900f
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mov x0, #ERRATA_MISSING
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.endif
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900:
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adr x1, \_cpu\()_cpu_str
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adr x2, \_cpu\()_errata_\_id\()_str
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bl errata_print_msg
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.endm
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#endif
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#endif /* __CPU_MACROS_S__ */
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