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https://github.com/ARM-software/arm-trusted-firmware.git
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1083b2b315
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <common_def.h>
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#include <tbbr/tbbr_img_def.h>
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#include <utils_def.h>
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#define PLATFORM_STACK_SIZE 0x1000
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT))
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/* topology */
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#define UNIPHIER_MAX_CPUS_PER_CLUSTER 4
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#define UNIPHIER_CLUSTER_COUNT 2
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#define PLATFORM_CORE_COUNT \
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((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT))
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#define PLAT_MAX_PWR_LVL U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define BL2_BASE ULL(0x80000000)
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#define BL2_LIMIT ULL(0x80080000)
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/* 0x80080000-0x81000000: reserved for DSP */
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#define UNIPHIER_SEC_DRAM_BASE 0x81000000ULL
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#define UNIPHIER_SEC_DRAM_LIMIT 0x82000000ULL
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#define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \
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(UNIPHIER_SEC_DRAM_BASE))
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#define BL31_BASE ULL(0x81000000)
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#define BL31_LIMIT ULL(0x81080000)
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#define BL32_BASE ULL(0x81080000)
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#define BL32_LIMIT ULL(0x81180000)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_XLAT_TABLES_DYNAMIC 1
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#define MAX_XLAT_TABLES 7
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#define MAX_MMAP_REGIONS 7
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#define MAX_IO_HANDLES 2
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#define MAX_IO_DEVICES 2
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#define MAX_IO_BLOCK_DEVICES 1
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#define TSP_SEC_MEM_BASE (BL32_BASE)
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#define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE))
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#define TSP_IRQ_SEC_PHY_TIMER 29
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#endif /* PLATFORM_DEF_H */
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