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https://github.com/ARM-software/arm-trusted-firmware.git
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1083b2b315
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
212 lines
6.1 KiB
C
212 lines
6.1 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <common_def.h>
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#include <tzc400.h>
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#include <utils.h>
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#include "ls_def.h"
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#define FIRMWARE_WELCOME_STR_LS1043 "Welcome to LS1043 BL1 Phase\n"
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#define FIRMWARE_WELCOME_STR_LS1043_BL2 "Welcome to LS1043 BL2 Phase\n"
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#define FIRMWARE_WELCOME_STR_LS1043_BL31 "Welcome to LS1043 BL31 Phase\n"
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#define FIRMWARE_WELCOME_STR_LS1043_BL32 "Welcome to LS1043 BL32 Phase, TSP\n"
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/* Required platform porting definitions */
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#define PLAT_PRIMARY_CPU 0x0
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#define PLAT_MAX_PWR_LVL LS_PWR_LVL1
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#define PLATFORM_CORE_COUNT 4
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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/*
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* Required LS standard platform porting definitions
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*/
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#define PLAT_LS_CLUSTER_COUNT 1
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#define PLAT_LS1043_CCI_CLUSTER0_SL_IFACE_IX 4
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#define LS1043_CLUSTER_COUNT 1
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#define LS1043_MAX_CPUS_PER_CLUSTER 4
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#define LS_DRAM1_BASE 0x80000000
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#define LS_DRAM2_BASE 0x880000000
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#define LS_DRAM2_SIZE 0x780000000 /* 30G */
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#define LS_DRAM1_SIZE 0x80000000 /* 2G */
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#define LS_NS_DRAM_BASE LS_DRAM1_BASE
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/* 64M Secure Memory, in fact there a 2M non-secure hole on top of it */
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#define LS_SECURE_DRAM_SIZE (64 * 1024 * 1024)
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#define LS_SECURE_DRAM_BASE (LS_NS_DRAM_BASE + LS_DRAM1_SIZE - \
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LS_SECURE_DRAM_SIZE)
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#define LS_NS_DRAM_SIZE (LS_DRAM1_SIZE - LS_SECURE_DRAM_SIZE)
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/*
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* By default, BL2 is in DDR memory.
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* If LS_BL2_IN_OCRAM is defined, BL2 will in OCRAM
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*/
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/* #define LS_BL2_IN_OCRAM */
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#ifndef LS_BL2_IN_OCRAM
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/*
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* on top of SECURE memory is 2M non-secure hole for OPTee,
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* 1M secure memory below this hole will be used for BL2.
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*/
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#define LS_BL2_DDR_BASE (LS_SECURE_DRAM_BASE + \
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LS_SECURE_DRAM_SIZE \
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- 3 * 1024 * 1024)
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#endif
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#define PLAT_LS_CCSR_BASE 0x1000000
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#define PLAT_LS_CCSR_SIZE 0xF000000
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/* Flash base address, currently ROM is not used for TF-A images on LS platforms */
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#define PLAT_LS_TRUSTED_ROM_BASE 0x60100000
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#define PLAT_LS_TRUSTED_ROM_SIZE 0x20000000 /* Flash size */
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#define PLAT_LS_FLASH_SIZE 0x20000000
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#define PLAT_LS_FLASH_BASE 0x60000000
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#define LS_SRAM_BASE 0x10000000
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#define LS_SRAM_LIMIT 0x10020000 /* 128K */
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#define LS_SRAM_SHARED_SIZE 0x1000 /* 4K */
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#define LS_SRAM_SIZE (LS_SRAM_LIMIT - LS_SRAM_BASE)
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#define LS_BL_RAM_BASE (LS_SRAM_BASE + LS_SRAM_SHARED_SIZE)
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#define PLAT_LS_FIP_MAX_SIZE 0x4000000
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/* Memory Layout */
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#define BL1_RO_BASE PLAT_LS_TRUSTED_ROM_BASE
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#define BL1_RO_LIMIT (PLAT_LS_TRUSTED_ROM_BASE \
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+ PLAT_LS_TRUSTED_ROM_SIZE)
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#define PLAT_LS_FIP_BASE 0x60120000
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#ifdef LS_BL2_IN_OCRAM
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/* BL2 is in OCRAM */
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#define PLAT_LS_MAX_BL1_RW_SIZE (52 * 1024) /* 52K */
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#define PLAT_LS_MAX_BL31_SIZE (64 * 1024) /* 64K */
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#define PLAT_LS_MAX_BL2_SIZE (44 * 1024) /* 44K */
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/* Reserve memory in OCRAM for BL31 Text and ROData segment */
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#define BL31_TEXT_RODATA_SIZE (32 * 1024) /* 32K */
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#else /* LS_BL2_IN_OCRAM */
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/* BL2 in DDR */
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#define PLAT_LS_MAX_BL1_RW_SIZE (64 * 1024) /* 64K */
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#define PLAT_LS_MAX_BL31_SIZE (64 * 1024) /* 64K */
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#define PLAT_LS_MAX_BL2_SIZE (1 * 1024 * 1024) /* 1M */
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#endif /* LS_BL2_IN_OCRAM */
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/*
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* Put BL31 at the start of OCRAM.
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*/
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#define BL31_BASE LS_SRAM_BASE
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#define BL31_LIMIT (LS_SRAM_BASE + PLAT_LS_MAX_BL31_SIZE)
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#ifdef LS_BL2_IN_OCRAM
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/*
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* BL2 follow BL31 Text and ROData region.
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*/
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#define BL2_BASE (BL31_BASE + BL31_TEXT_RODATA_SIZE)
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#define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
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#else
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/*
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* BL2 in DDR memory.
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*/
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#define BL2_BASE LS_BL2_DDR_BASE
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#define BL2_LIMIT (BL2_BASE + PLAT_LS_MAX_BL2_SIZE)
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#endif
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/*
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* Put BL1 RW at the top of the Trusted SRAM.
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*/
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#ifdef LS_BL2_IN_OCRAM
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#define BL1_RW_BASE BL2_LIMIT
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#else
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#define BL1_RW_BASE BL31_LIMIT
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#endif
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#define BL1_RW_LIMIT LS_SRAM_LIMIT
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/* Put BL32 in secure memory */
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#define BL32_BASE LS_SECURE_DRAM_BASE
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#define BL32_LIMIT (LS_SECURE_DRAM_BASE + LS_SECURE_DRAM_SIZE)
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/* BL33 memory region */
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#define BL33_BASE 0x82000000
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#define BL33_LIMIT (LS_NS_DRAM_BASE + LS_NS_DRAM_SIZE)
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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/*
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* On ARM standard platforms, the TSP can execute from Trusted SRAM,
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* Trusted DRAM (if available) or the DRAM region secured by the TrustZone
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* controller.
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*/
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#define TSP_SEC_MEM_BASE BL32_BASE
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#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE)
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/*
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* ID of the secure physical generic timer interrupt used by the TSP.
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*/
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#define TSP_IRQ_SEC_PHY_TIMER 29
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/*
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* GIC related constants
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*/
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#define PLAT_LS1043_CCI_BASE 0x01180000
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#define GICD_BASE 0x01401000
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#define GICC_BASE 0x01402000
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#define GICD_BASE_64K 0x01410000
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#define GICC_BASE_64K 0x01420000
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#define DCFG_CCSR_SVR 0x1ee00a4
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#define REV1_0 0x10
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#define REV1_1 0x11
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#define GIC_ADDR_BIT 31
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#define SCFG_GIC400_ALIGN 0x1570188
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/* UART related definition */
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#define PLAT_LS1043_DUART1_BASE 0x021c0000
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#define PLAT_LS1043_DUART2_BASE 0x021d0000
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#define PLAT_LS1043_DUART_SIZE 0x10000
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#define PLAT_LS1043_UART_BASE 0x21c0500
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#define PLAT_LS1043_UART2_BASE 0x21c0600
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#define PLAT_LS1043_UART_CLOCK 400000000
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#define PLAT_LS1043_UART_BAUDRATE 115200
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/* Define UART to be used by TF-A log */
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#define LS_TF_UART_BASE PLAT_LS1043_UART_BASE
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#define LS_TF_UART_CLOCK PLAT_LS1043_UART_CLOCK
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#define LS_TF_UART_BAUDRATE PLAT_LS1043_UART_BAUDRATE
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#define LS1043_SYS_CNTCTL_BASE 0x2B00000
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL1)
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#define PLATFORM_STACK_SIZE 0x440
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#define MAX_MMAP_REGIONS 6
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#define MAX_XLAT_TABLES 4
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#elif defined(IMAGE_BL2)
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#define PLATFORM_STACK_SIZE 0x400
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#define MAX_MMAP_REGIONS 8
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#define MAX_XLAT_TABLES 6
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#elif defined(IMAGE_BL31)
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#define PLATFORM_STACK_SIZE 0x400
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#define MAX_MMAP_REGIONS 8
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#define MAX_XLAT_TABLES 4
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#elif defined(IMAGE_BL32)
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#define PLATFORM_STACK_SIZE 0x440
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#define MAX_MMAP_REGIONS 8
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#define MAX_XLAT_TABLES 9
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#endif
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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#endif /* PLATFORM_DEF_H */
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