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https://github.com/ARM-software/arm-trusted-firmware.git
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1083b2b315
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
94 lines
3.3 KiB
C
94 lines
3.3 KiB
C
/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef JUNO_DEF_H
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#define JUNO_DEF_H
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#include <utils_def.h>
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/*******************************************************************************
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* Juno memory map related constants
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******************************************************************************/
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/* Board revisions */
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#define REV_JUNO_R0 0x1 /* Rev B */
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#define REV_JUNO_R1 0x2 /* Rev C */
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#define REV_JUNO_R2 0x3 /* Rev D */
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/* Bypass offset from start of NOR flash */
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#define BL1_ROM_BYPASS_OFFSET 0x03EC0000
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#define EMMC_BASE 0x0c000000
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#define EMMC_SIZE 0x04000000
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#define PSRAM_BASE 0x14000000
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#define PSRAM_SIZE 0x02000000
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#define JUNO_SSC_VER_PART_NUM 0x030
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/*******************************************************************************
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* Juno topology related constants
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******************************************************************************/
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#define JUNO_CLUSTER_COUNT 2
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#define JUNO_CLUSTER0_CORE_COUNT 2
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#define JUNO_CLUSTER1_CORE_COUNT 4
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/*******************************************************************************
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* TZC-400 related constants
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******************************************************************************/
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#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */
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#define TZC400_NSAID_PCIE 1
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#define TZC400_NSAID_HDLCD0 2
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#define TZC400_NSAID_HDLCD1 3
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#define TZC400_NSAID_USB 4
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#define TZC400_NSAID_DMA330 5
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#define TZC400_NSAID_THINLINKS 6
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#define TZC400_NSAID_AP 9
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#define TZC400_NSAID_GPU 10
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#define TZC400_NSAID_SCP 11
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#define TZC400_NSAID_CORESIGHT 12
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/*******************************************************************************
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* TRNG related constants
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******************************************************************************/
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#define TRNG_BASE 0x7FE60000ULL
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#define TRNG_NOUTPUTS 4
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#define TRNG_STATUS 0x10
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#define TRNG_INTMASK 0x14
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#define TRNG_CONFIG 0x18
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#define TRNG_CONTROL 0x1C
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#define TRNG_NBYTES 16 /* Number of bytes generated per round. */
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/*******************************************************************************
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* MMU-401 related constants
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******************************************************************************/
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#define MMU401_SSD_OFFSET 0x4000
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#define MMU401_DMA330_BASE 0x7fb00000
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/*******************************************************************************
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* Interrupt handling constants
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******************************************************************************/
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#define JUNO_IRQ_DMA_SMMU 126
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#define JUNO_IRQ_HDLCD0_SMMU 128
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#define JUNO_IRQ_HDLCD1_SMMU 130
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#define JUNO_IRQ_USB_SMMU 132
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#define JUNO_IRQ_THIN_LINKS_SMMU 134
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#define JUNO_IRQ_SEC_I2C 137
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#define JUNO_IRQ_GPU_SMMU_1 73
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#define JUNO_IRQ_ETR_SMMU 75
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/*******************************************************************************
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* Memprotect definitions
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******************************************************************************/
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/* PSCI memory protect definitions:
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* This variable is stored in a non-secure flash because some ARM reference
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* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
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* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#endif /* JUNO_DEF_H */
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