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1083b2b315
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <common_def.h>
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#include <sunxi_mmap.h>
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#include <tbbr/tbbr_img_def.h>
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#include <utils_def.h>
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#define BL31_BASE SUNXI_SRAM_A2_BASE
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#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE)
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/* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */
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#define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20))
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define MAX_MMAP_REGIONS (4 + PLATFORM_MMAP_REGIONS)
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#define MAX_XLAT_TABLES 2
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#define PLAT_MAX_PWR_LVL_STATES U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_NUM_PWR_DOMAINS (1 + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
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#define PLATFORM_MMAP_REGIONS 3
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#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
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#ifndef SPD_none
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#ifndef BL32_BASE
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#define BL32_BASE SUNXI_DRAM_BASE
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#endif
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#endif
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#endif /* PLATFORM_DEF_H */
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