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b225926181
Currently SGI interrupts are not received in secondary cores because of issue in GIC configuration. In current Versal NET specific GIC functions, redistributor configuration is not happening properly. Because of that SGI interrupt from one processor to another processor is not transferring. So, use common GIC handlers which will iterate over all GIC redistributor frames and discovers per cpu redistributor frame. Also, it initializes corresponding interface in GICv3. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: I1433260b8520d6a315fdf5df86bd0688f92d211a
79 lines
2.4 KiB
ArmAsm
79 lines
2.4 KiB
ArmAsm
/*
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* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <drivers/arm/gicv3.h>
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#include <platform_def.h>
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.globl plat_arm_calc_core_pos
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl platform_mem_init
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.globl plat_my_core_pos
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* TODO: Should we read the PSYS register to make sure
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* that the request has gone through.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mrs x0, mpidr_el1
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/*
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* There is no sane reason to come out of this wfi. This
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* cpu will be powered on and reset by the cpu_on pm api
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*/
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dsb sy
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bl plat_panic_handler
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endfunc plat_secondary_cold_boot_setup
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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cmp x0, #VERSAL_NET_PRIMARY_CPU
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cset x0, eq
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ret x9
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the plat_core_pos_by_mpidr()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_core_pos_by_mpidr
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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* This function uses the plat_core_pos_by_mpidr()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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b plat_core_pos_by_mpidr
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endfunc plat_arm_calc_core_pos
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/* ---------------------------------------------------------------------
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* We don't need to carry out any memory initialization on Versal NET
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* platform. The Secure RAM is accessible straight away.
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* ---------------------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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