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https://github.com/ARM-software/arm-trusted-firmware.git
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4087ed6c12
Currently, the registers which are maintained per-world, does not take into account the reset value while configuring the context for the respective world. This leads to an issue, wherein the register retains the same value across world switch, which is an error. This patch addresses this problem, by configuring the register (cptr_el3) precisely according to the world, the cpu is in execution via resetting it before initializing the world specific context. Change-Id: I592d82af373155fca67eed109c199341c305f0b9 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
/*
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* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CONTEXT_MGMT_H
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#define CONTEXT_MGMT_H
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#include <assert.h>
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#include <context.h>
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#include <stdint.h>
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#include <arch.h>
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/*******************************************************************************
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* Forward declarations
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******************************************************************************/
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struct entry_point_info;
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/*******************************************************************************
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* Function & variable prototypes
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******************************************************************************/
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void cm_init(void);
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void *cm_get_context_by_index(unsigned int cpu_idx,
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unsigned int security_state);
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void cm_set_context_by_index(unsigned int cpu_idx,
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void *context,
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unsigned int security_state);
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void *cm_get_context(uint32_t security_state);
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void cm_set_context(void *context, uint32_t security_state);
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void cm_init_my_context(const struct entry_point_info *ep);
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void cm_init_context_by_index(unsigned int cpu_idx,
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const struct entry_point_info *ep);
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void cm_setup_context(cpu_context_t *ctx, const struct entry_point_info *ep);
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void cm_prepare_el3_exit(uint32_t security_state);
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void cm_prepare_el3_exit_ns(void);
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#ifdef __aarch64__
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#if IMAGE_BL31
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void cm_manage_extensions_el3(void);
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void manage_extensions_nonsecure_per_world(void);
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void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx);
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#endif
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#if CTX_INCLUDE_EL2_REGS
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void cm_el2_sysregs_context_save(uint32_t security_state);
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void cm_el2_sysregs_context_restore(uint32_t security_state);
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#endif
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void cm_el1_sysregs_context_save(uint32_t security_state);
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void cm_el1_sysregs_context_restore(uint32_t security_state);
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void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint);
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void cm_set_elr_spsr_el3(uint32_t security_state,
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uintptr_t entrypoint, uint32_t spsr);
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void cm_write_scr_el3_bit(uint32_t security_state,
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uint32_t bit_pos,
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uint32_t value);
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void cm_set_next_eret_context(uint32_t security_state);
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u_register_t cm_get_scr_el3(uint32_t security_state);
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/* Inline definitions */
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/*******************************************************************************
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* This function is used to program the context that's used for exception
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* return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
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* the required security state
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******************************************************************************/
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static inline void cm_set_next_context(void *context)
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{
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#if ENABLE_ASSERTIONS
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uint64_t sp_mode;
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/*
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* Check that this function is called with SP_EL0 as the stack
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* pointer
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*/
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__asm__ volatile("mrs %0, SPSel\n"
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: "=r" (sp_mode));
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assert(sp_mode == MODE_SP_EL0);
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#endif /* ENABLE_ASSERTIONS */
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__asm__ volatile("msr spsel, #1\n"
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"mov sp, %0\n"
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"msr spsel, #0\n"
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: : "r" (context));
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}
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#else
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void *cm_get_next_context(void);
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void cm_set_next_context(void *context);
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static inline void cm_manage_extensions_el3(void) {}
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static inline void manage_extensions_nonsecure_per_world(void) {}
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#endif /* __aarch64__ */
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#endif /* CONTEXT_MGMT_H */
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