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https://github.com/ARM-software/arm-trusted-firmware.git
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4225ce8b87
Define default SD buffer address and size in DRAM. Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I5872d95b0c1114e05f0e145756e9a6ef39b2fd9a
172 lines
3.8 KiB
C
172 lines
3.8 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_DEFAULT_DEF_H
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#define PLAT_DEFAULT_DEF_H
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/*
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* Platform binary types for linking
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*/
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#ifdef __aarch64__
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#else
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#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
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#define PLATFORM_LINKER_ARCH arm
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#endif /* __aarch64__ */
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#define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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/* NXP Platforms have DRAM divided into banks.
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* DRAM0 Bank: Maximum size of this bank is fixed to 2GB
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* DRAM1 Bank: Greater than 2GB belongs to bank1 and size of bank1 varies from
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* one platform to other platform.
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* DRAMn Bank:
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*
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* Except a few, all the platforms have 2GB size as DRAM0 BANK.
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* Hence common for all the platforms.
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* For platforms where DRAM0 Size is < 2GB, it is defined in platform_def.h
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*/
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#ifndef PLAT_DEF_DRAM0_SIZE
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#define PLAT_DEF_DRAM0_SIZE 0x80000000 /* 2G */
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#endif
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/* This is common for all platforms where: */
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#ifndef NXP_NS_DRAM_ADDR
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#define NXP_NS_DRAM_ADDR NXP_DRAM0_ADDR
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#endif
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/* 1 MB is reserved for dma of sd */
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#ifndef NXP_SD_BLOCK_BUF_SIZE
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#define NXP_SD_BLOCK_BUF_SIZE (1 * 1024 * 1024)
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#endif
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/* 64MB is reserved for Secure memory */
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#ifndef NXP_SECURE_DRAM_SIZE
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#define NXP_SECURE_DRAM_SIZE (64 * 1024 * 1024)
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#endif
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/* 2M Secure EL1 Payload Shared Memory */
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#ifndef NXP_SP_SHRD_DRAM_SIZE
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#define NXP_SP_SHRD_DRAM_SIZE (2 * 1024 * 1024)
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#endif
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#ifndef NXP_NS_DRAM_SIZE
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/* Non secure memory */
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#define NXP_NS_DRAM_SIZE (PLAT_DEF_DRAM0_SIZE - \
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(NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE))
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#endif
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#ifndef NXP_SD_BLOCK_BUF_ADDR
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#define NXP_SD_BLOCK_BUF_ADDR (NXP_NS_DRAM_ADDR)
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#endif
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#ifndef NXP_SECURE_DRAM_ADDR
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#ifdef TEST_BL31
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#define NXP_SECURE_DRAM_ADDR 0
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#else
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#define NXP_SECURE_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE - \
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(NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE))
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#endif
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#endif
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#ifndef NXP_SP_SHRD_DRAM_ADDR
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#define NXP_SP_SHRD_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE - \
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NXP_SP_SHRD_DRAM_SIZE)
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#endif
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#ifndef BL31_BASE
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/* 2 MB reserved in secure memory for DDR */
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#define BL31_BASE NXP_SECURE_DRAM_ADDR
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#endif
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#ifndef BL31_SIZE
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#define BL31_SIZE (0x200000)
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#endif
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#ifndef BL31_LIMIT
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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#endif
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/* Put BL32 in secure memory */
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#ifndef BL32_BASE
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#define BL32_BASE (NXP_SECURE_DRAM_ADDR + BL31_SIZE)
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#endif
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#ifndef BL32_LIMIT
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#define BL32_LIMIT (NXP_SECURE_DRAM_ADDR + \
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NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)
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#endif
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/* BL33 memory region */
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/* Hardcoded based on current address in u-boot */
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#ifndef BL33_BASE
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#define BL33_BASE 0x82000000
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#endif
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#ifndef BL33_LIMIT
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#define BL33_LIMIT (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE)
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#endif
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/*
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* FIP image defines - Offset at which FIP Image would be present
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* Image would include Bl31 , Bl33 and Bl32 (optional)
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*/
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#ifdef POLICY_FUSE_PROVISION
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#ifndef FUSE_BUF
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#define FUSE_BUF ULL(0x81000000)
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#endif
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#ifndef FUSE_SZ
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#define FUSE_SZ 0x80000
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#endif
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#endif
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#ifndef MAX_FIP_DEVICES
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#define MAX_FIP_DEVICES 2
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#endif
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#ifndef PLAT_FIP_OFFSET
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#define PLAT_FIP_OFFSET 0x100000
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#endif
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#ifndef PLAT_FIP_MAX_SIZE
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#define PLAT_FIP_MAX_SIZE 0x400000
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#endif
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/* Check if this size can be determined from array size */
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#if defined(IMAGE_BL2)
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#ifndef MAX_MMAP_REGIONS
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#define MAX_MMAP_REGIONS 8
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#endif
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#ifndef MAX_XLAT_TABLES
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#define MAX_XLAT_TABLES 6
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#endif
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#elif defined(IMAGE_BL31)
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#ifndef MAX_MMAP_REGIONS
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#define MAX_MMAP_REGIONS 9
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#endif
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#ifndef MAX_XLAT_TABLES
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#define MAX_XLAT_TABLES 9
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#endif
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#elif defined(IMAGE_BL32)
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#ifndef MAX_MMAP_REGIONS
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#define MAX_MMAP_REGIONS 8
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#endif
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#ifndef MAX_XLAT_TABLES
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#define MAX_XLAT_TABLES 9
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#endif
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#endif
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/*
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* ID of the secure physical generic timer interrupt used by the BL32.
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*/
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#ifndef BL32_IRQ_SEC_PHY_TIMER
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#define BL32_IRQ_SEC_PHY_TIMER 29
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#endif
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#endif /* PLAT_DEFAULT_DEF_H */
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