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https://github.com/ARM-software/arm-trusted-firmware.git
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245 lines
8.2 KiB
C
245 lines
8.2 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <memctrl.h>
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#include <memctrl_v1.h>
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#include <mmio.h>
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#include <string.h>
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#include <tegra_def.h>
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#include <utils.h>
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#include <xlat_tables_v2.h>
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#define TEGRA_GPU_RESET_REG_OFFSET 0x28c
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#define GPU_RESET_BIT (1 << 24)
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/* Video Memory base and size (live values) */
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static uint64_t video_mem_base;
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static uint64_t video_mem_size;
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/*
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* Init SMMU.
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*/
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void tegra_memctrl_setup(void)
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{
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/*
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* Setup the Memory controller to allow only secure accesses to
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* the TZDRAM carveout
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*/
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INFO("Tegra Memory Controller (v1)\n");
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/* allow translations for all MC engines */
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0,
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(unsigned int)MC_SMMU_TRANSLATION_ENABLE);
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tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY);
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tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL);
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tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL);
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/* flush PTC and TLB */
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tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL);
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(void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
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tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL);
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/* enable SMMU */
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tegra_mc_write_32(MC_SMMU_CONFIG_0,
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MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE);
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(void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
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/* video memory carveout */
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
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(uint32_t)(video_mem_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
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}
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/*
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* Restore Memory Controller settings after "System Suspend"
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*/
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void tegra_memctrl_restore_settings(void)
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{
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tegra_memctrl_setup();
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}
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/*
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* Secure the BL31 DRAM aperture.
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*
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* phys_base = physical base of TZDRAM aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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/*
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* Setup the Memory controller to allow only secure accesses to
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* the TZDRAM carveout
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*/
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INFO("Configuring TrustZone DRAM Memory Carveout\n");
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tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base);
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tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
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}
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/*
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* Secure the BL31 TZRAM aperture.
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*
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* phys_base = physical base of TZRAM aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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/*
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* The v1 hardware controller does not have any registers
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* for setting up the on-chip TZRAM.
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*/
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}
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static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
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unsigned long long non_overlap_area_size)
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{
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/*
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* Map the NS memory first, clean it and then unmap it.
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*/
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mmap_add_dynamic_region(non_overlap_area_start, /* PA */
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non_overlap_area_start, /* VA */
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non_overlap_area_size, /* size */
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MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
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zeromem((void *)non_overlap_area_start, non_overlap_area_size);
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flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
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mmap_remove_dynamic_region(non_overlap_area_start,
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non_overlap_area_size);
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}
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/*
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* Program the Video Memory carveout region
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*
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* phys_base = physical base of aperture
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* size_in_bytes = size of aperture in bytes
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*/
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void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
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{
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uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20);
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uintptr_t vmem_end_new = phys_base + size_in_bytes;
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uint32_t regval;
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unsigned long long non_overlap_area_size;
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/*
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* The GPU is the user of the Video Memory region. In order to
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* transition to the new memory region smoothly, we program the
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* new base/size ONLY if the GPU is in reset mode.
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*/
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regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);
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if ((regval & GPU_RESET_BIT) == 0) {
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ERROR("GPU not in reset! Video Memory setup failed\n");
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return;
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}
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/*
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* Setup the Memory controller to restrict CPU accesses to the Video
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* Memory region
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*/
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INFO("Configuring Video Memory Carveout\n");
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/*
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* Configure Memory Controller directly for the first time.
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*/
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if (video_mem_base == 0)
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goto done;
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/*
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* Clear the old regions now being exposed. The following cases
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* can occur -
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*
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* 1. clear whole old region (no overlap with new region)
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* 2. clear old sub-region below new base
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* 3. clear old sub-region above new end
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*/
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INFO("Cleaning previous Video Memory Carveout\n");
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if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) {
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tegra_clear_videomem(video_mem_base, video_mem_size << 20);
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} else {
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if (video_mem_base < phys_base) {
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non_overlap_area_size = phys_base - video_mem_base;
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tegra_clear_videomem(video_mem_base, non_overlap_area_size);
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}
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if (vmem_end_old > vmem_end_new) {
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non_overlap_area_size = vmem_end_old - vmem_end_new;
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tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
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}
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}
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done:
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32));
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
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/* store new values */
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video_mem_base = phys_base;
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video_mem_size = size_in_bytes >> 20;
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}
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/*
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* During boot, USB3 and flash media (SDMMC/SATA) devices need access to
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* IRAM. Because these clients connect to the MC and do not have a direct
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* path to the IRAM, the MC implements AHB redirection during boot to allow
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* path to IRAM. In this mode, accesses to a programmed memory address aperture
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* are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
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* is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
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* initialized to disable this aperture.
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*
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* Once bootup is complete, we must program IRAM base to 0xffffffff and
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* IRAM top to 0x00000000, thus disabling access to IRAM. DRAM is then
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* potentially accessible in this address range. These aperture registers
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* also have an access_control/lock bit. After disabling the aperture, the
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* access_control register should be programmed to lock the registers.
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*/
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void tegra_memctrl_disable_ahb_redirection(void)
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{
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/* program the aperture registers */
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tegra_mc_write_32(MC_IRAM_BASE_LO, 0xFFFFFFFF);
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tegra_mc_write_32(MC_IRAM_TOP_LO, 0);
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tegra_mc_write_32(MC_IRAM_BASE_TOP_HI, 0);
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/* lock the aperture registers */
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tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES);
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}
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