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cedfa04ba5
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the size of translation tables by increasing the maximum permitted value of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and VSTCR_EL2. This feature is supported in AArch64 state only. This patch adds support for this feature to both versions of the translation tables library. It also removes the static build time checks for virtual address space size checks to runtime assertions. Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
110 lines
3 KiB
C
110 lines
3 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef XLAT_TABLES_PRIVATE_H
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#define XLAT_TABLES_PRIVATE_H
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#include <stdbool.h>
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#include <platform_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#if PLAT_XLAT_TABLES_DYNAMIC
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/*
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* Private shifts and masks to access fields of an mmap attribute
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*/
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/* Dynamic or static */
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#define MT_DYN_SHIFT U(31)
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/*
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* Memory mapping private attributes
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*
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* Private attributes not exposed in the public header.
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*/
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/*
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* Regions mapped before the MMU can't be unmapped dynamically (they are
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* static) and regions mapped with MMU enabled can be unmapped. This
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* behaviour can't be overridden.
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*
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* Static regions can overlap each other, dynamic regions can't.
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*/
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#define MT_STATIC (U(0) << MT_DYN_SHIFT)
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#define MT_DYNAMIC (U(1) << MT_DYN_SHIFT)
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#endif /* PLAT_XLAT_TABLES_DYNAMIC */
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extern uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
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/*
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* Return the execute-never mask that will prevent instruction fetch at the
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* given translation regime.
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*/
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uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime);
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/*
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* Invalidate all TLB entries that match the given virtual address. This
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* operation applies to all PEs in the same Inner Shareable domain as the PE
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* that executes this function. This functions must be called for every
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* translation table entry that is modified. It only affects the specified
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* translation regime.
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*
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* Note, however, that it is architecturally UNDEFINED to invalidate TLB entries
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* pertaining to a higher exception level, e.g. invalidating EL3 entries from
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* S-EL1.
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*/
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void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime);
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/*
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* This function has to be called at the end of any code that uses the function
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* xlat_arch_tlbi_va().
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*/
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void xlat_arch_tlbi_va_sync(void);
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/* Print VA, PA, size and attributes of all regions in the mmap array. */
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void xlat_mmap_print(const mmap_region_t *mmap);
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/*
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* Print the current state of the translation tables by reading them from
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* memory.
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*/
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void xlat_tables_print(xlat_ctx_t *ctx);
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/*
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* Returns a block/page table descriptor for the given level and attributes.
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*/
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uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr,
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unsigned long long addr_pa, unsigned int level);
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/*
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* Architecture-specific initialization code.
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*/
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/* Returns the current Exception Level. The returned EL must be 1 or higher. */
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unsigned int xlat_arch_current_el(void);
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/*
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* Return the maximum physical address supported by the hardware.
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* This value depends on the execution state (AArch32/AArch64).
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*/
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unsigned long long xlat_arch_get_max_supported_pa(void);
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/*
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* Returns true if the MMU of the translation regime managed by the given
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* xlat_ctx_t is enabled, false otherwise.
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*/
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bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx);
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/* Returns true if the data cache is enabled at the current EL. */
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bool is_dcache_enabled(void);
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/*
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* Returns minimum virtual address space size supported by the architecture
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*/
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uintptr_t xlat_get_min_virt_addr_space_size(void);
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#endif /* XLAT_TABLES_PRIVATE_H */
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