johpow01 0e0521bdfc Workaround for Neoverse N1 erratum 1800710 ... Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6		2020-06-25 19:58:35 +00:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	Cleanup the code for TBBR CoT descriptors	2020-05-19 05:05:19 +01:00
cpu-specific-build-macros.rst	Workaround for Neoverse N1 erratum 1800710	2020-06-25 19:58:35 +00:00
firmware-design.rst	doc: Fixup some SMCCC links	2020-04-17 14:06:54 +02:00
index.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
interrupt-framework-design.rst	docs: Update SMCCC doc, other changes for release	2020-04-16 10:03:39 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
trusted-board-boot-build.rst	Mention COT build option in trusted-board-boot-build.rst	2020-03-12 17:11:26 +01:00
trusted-board-boot.rst	Update cryptographic algorithms in TBBR doc	2020-03-12 17:11:25 +01:00